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參數(shù)資料
| 型號： | 7640 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE |
| 中文描述： | 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00 |
| 文件頁數(shù)： | 45/97頁 |
| 文件大小： | 1885K |
| 代理商： | 7640 |
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44
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reserved
OER
FER
PER
RBF
TBE
TCM
MSB
7
LSB
0
Address: 0032
,003A
16
Access: Read only
Reset: 03
16
SER
TCM
Transmission complete (Transmission Register empty) Flag (Bit 0)
0: Data in Transmission Register
1: No data in Transmission Register
TX Buffer Empty flag (Bit 1)
0: Data in TX Buffer
1: No data in the TX Buffer
RX Buffer Full Flag (Bit 2)
0: No data in RX Buffer
1: Data in RX Buffer
Receive Parity Error Flag (Bit 3)
0: No parity error received
1: Received framing error
Receive Framing Error Flag (Bit 4)
0: No framing error received
1: Received framing error
Receive Overrun Flag (Bit 5)
0: No overrun receive received
1: Received overrun
Receive Error Sum flag (Bit 6)
0: No error received
1: Received error
Reserved (Read “0”)
TBE
RBF
PER
FER
OER
SER
Bit 7
Fig. 1.44. UART Status Register (U1STS, U2STS)
1.19.4 Transmit/Receive Methods
1.19.4.1 Transmit Method
Setup
Define the baud rate by writing a value from 0-255 into
the UxBRG (see Figure 1.45).
Set the Transmission Initialization Bit (TIN, bit 2 of
UxCON), to “1”. This will reset the transmit status to a
value of 03
16
.
Select the interrupt source to be either TBE or TCM
by clearing or setting the Transmit Interrupt Source Se-
lection Bit (TIS, bit 4 of UxCON).
Configure the data format and clock selection by writ-
ing the appropriate value to UxMOD.
Set the Clear-To-Send Enable Bit (CTS_SEL, bit 5 of
UxCON), if CTS handshaking will be used.
Set the Transmit Enable Bit (TEN, bit 0 of UxCON), to
“1”.
Operation
When data is written to the low-order byte of the trans-
mit buffer (UxTRB1), TBE is cleared to “0”. If 9-bit
character length has been selected, the high-order byte
of the transmit buffer (UxTRB2) should be written before
the low-order byte (UxTRB1).
If no data is being shifted out of the transmit shift reg-
ister and CTS handshaking is disabled, the data written
to the transmit buffer is transferred to the transmit shift
register and the TCM flag in UxSTS is cleared to a “0”.
In addition, the TBE flag is set to a “1”, signaling that
the next byte of data can be written to the transmit
buffer. If CTS handshaking is enabled, the operation de-
scribed above does not take place until CTSx is
brought low.
Data from the transmit shift register is transmitted one
bit at a time beginning with the start bit and ending with
the stop bit. Note that the LSB is transmitted first.
If the TEN bit is cleared to a “0” while data is still be-
ing transmitted, the transmitter will continue until the
last bit is sent. This is also the case when CTS hand-
shaking is enabled and CTSx is brought back high
during transmission.
When the last bit is transmitted, the TCM flag is set to
a “1” if the transmit buffer is empty, TEN is a “0”, or
CTS handshaking is enabled and CTSx is “1”. If the
transmit buffer is not empty, TEN is a “1”, and CTS
handshaking is disabled or CTS handshaking is en-
abled and CTSx is low, the TCM flag is not set
because transfer of the contents of the transmit buffer
to the transmit shift register occurs immediately.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 7641 | 7641 Group Datasheet Datasheet 2145K/MAR.26.02 |
| 7643 | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 765-11-(SERIES) | Analog IC |
| 765-11-20K | Analog IC |
| 765-11-25A | Analog IC |
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