參數(shù)資料
型號： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁數(shù)： 52/97頁
文件大?。?/td> 1885K
代理商： 7640
51
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.21.2 USB Interrupts
There are two types of USB interrupts in this device.
USB function (including overrun/underrun, reset, sus-
pend and resume) interrupt, which is used to control
the flow of data.
The second type is start-of-frame (SOF) interrupt,
which is used to monitor the transfer of isochronous
(ISO) data.
1.21.2.1 USB Function Interrupts
Endpoints 1-4 each have two interrupt status flags as-
sociated with them to control data transfer or to report
a STALL/UNDER_RUN/OVER_RUN condition. The
USB Endpoint x Out Interrupt Status Flag is set when
the USB FCU successfully receives a packet of data,
or the USB FCU sets the FORCE_STALL bit or the
OVER_RUN bit of the Endpoint x OUT CSR. The
USB Endpoint x In Interrupt Status Flag is set when
the USB FCU successfully sends a packet of data or
sets the UNDER_RUN bit of the Endpoint x IN CSR.
Endpoint 0 (the control endpoint) has one interrupt
status bit associated with it to control data transfer or
report a STALL condition. The USB Endpoint 0 Inter-
rupt Status Flag is set when the USB FCU
successfully receives/sends a packet of data, sets the
SETUP_END bit or the FORCE_STALL bit, or clears
the DATA_END bit in the Endpoint 0 IN CSR. Each
endpoint interrupt is enabled by setting the corre-
sponding bit in the USB Interrupt Enable Register 1
and 2 (see Figure 1.57 and Figure 1.58). The USB In-
terrupt Status Register 1 and 2, shown in Figure 1.55
and Figure 1.56, are used to indicate pending inter-
rupts for a given endpoint. The USB FCU sets the
interrupt status bits. The CPU writes a “1” to clear the
corresponding status bit. By writing back the same
value it read, the CPU will clear all the existing inter-
rupts. The CPU must read then write both status
registers, writing status register 1 first and status reg-
ister 2 second to guarantee proper operation.
The Suspend Signaling Interrupt Status Flag is set if
the USB FCU does not detect any bus activity on D+/
D- for at least 3ms. The Resume Signaling Interrupt
Status Flag is set when a USB FCU is in the suspend
state and detects non-idle signaling on D+/D-. There
is an interrupt enable bit for the suspend interrupt (bit
7 of Interrupt Enable Register 2), but not one for the
resume interrupt. The resume interrupt is always en-
abled.
The USB Reset Interrupt Status Flag is set if the USB
FCU sees a SE0 present on D+/D- for at least 2.5ms.
When this bit is set, all USB internal registers (except
for this bit) are reset to their default values. This bit is
cleared by the CPU writing a “1” to it. When the CPU
detects a USB reset interrupt, it needs to re-initialize
the USB FCU in order for it to accept packets from
the host. The USB reset interrupt is always enabled.
The Overrun/Underrun Interrupt Status Flag is set
(applicable to endpoints used for isochronous data
transfer) when an overrun condition occurs in an end-
point (CPU is too slow to unload the data from the
FIFO), or when an underrun condition occurs in an
endpoint (CPU is too slow to load the data to the
FIFO).
The USB Function Interrupt (sum of all individual
function interrupts) is enabled by setting bit 0 of Inter-
rupt Control Register A (ICONA) to a “1”.
1.21.2.2 USB SOF Interrupt
The USB SOF (Start-Of-Frame) interrupt is used to
control the transfer of isochronous data. The USB
FCU generates a start-of-frame interrupt when a
start-of-frame packet is received. The USB SOF inter-
rupt is enabled by setting bit 1 of ICONA to a “1”.
1.21.3 USB Endpoint FIFOs
The USB FCU has an IN (transmit) FIFO and an OUT
(receive) FIFO for each endpoint. Each endpoint (ex-
cept endpoint 0) can be configured to support both
single packet mode (only a single data packet is al-
lowed to reside in the endpoint’s FIFO) or dual packet
mode (up to two data packets are allowed to reside in
the endpoint’s FIFO), which provides support for
back-to-back transmission or back-to-back reception.
The mode configuration is automatically set by the
MAXP value. When MAXP > 1/2 of the endpoint’s
FIFO size, single packet mode is set. When MAXP <=
1/2 of the endpoint’s FIFO size, dual packet mode is
set.
Throughout this specification, the terms “IN FIFO”
and “OUT FIFO” refer to the FIFOs associated with
the current endpoint as specified by the Endpoint In-
dex Register.
In the event of a bad transmission/reception, the USB
FCU handles all the read/write pointer reversal and
data set management tasks when it is applicable.
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
76400 制造商:AMP 功能描述:76400 AMPHENOL NXF4C 制造商:TE Connectivity 功能描述:
76-400 制造商:AMP 功能描述:76400 AMPHENOL NXF4C
764-00/001 功能描述:MULTI FUNCT MOD SCREW C14 SWITCH RoHS:是 類別:連接器，互連式 >> 電源輸入 - 輸入端，輸出端，模塊 系列:764 標(biāo)準(zhǔn)包裝:50 系列:FELCOM 連接器類型:IEC 320-C14 連接器類型:插座，公引腳 - 模塊 位置數(shù):3 電流:10A 電壓:250V 安裝類型:面板安裝，卡入式；通孔 端接類型:焊接 保險(xiǎn)絲盒:包括在內(nèi) 特點(diǎn):保險(xiǎn)絲盒
764-00/002 功能描述:交流電源輸入模塊 Screw Mnt Solder RoHS:否 制造商:Schurter 過濾:Yes 過濾器類型:IEC Inlet Filters 產(chǎn)品:Inlets 電流額定值:4 A 電壓額定值:250 VAC 外殼材料:Thermoplastic 安裝風(fēng)格:Panel, Screw 端接類型:Quick Connect 工作溫度范圍:- 25 C to + 85 C 連接器類型:C-14
764-00/003 功能描述:交流電源輸入模塊 SWITCHING AC RECPT RoHS:否 制造商:Schurter 過濾:Yes 過濾器類型:IEC Inlet Filters 產(chǎn)品:Inlets 電流額定值:4 A 電壓額定值:250 VAC 外殼材料:Thermoplastic 安裝風(fēng)格:Panel, Screw 端接類型:Quick Connect 工作溫度范圍:- 25 C to + 85 C 連接器類型:C-14
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*