參數(shù)資料
型號(hào)： 7640
英文描述： IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-PDIP, TUBE
中文描述： 7640組數(shù)據(jù)表數(shù)據(jù)表1885K/SEP.05.00
文件頁(yè)數(shù)： 19/97頁(yè)
文件大?。?/td> 1885K
代理商： 7640
18
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Direction Register
Pull-up Control
Data Bus
Port Latch
Key-on Wake up Input
1.14.1 I/O Ports
This device has 66 programmable I/O pins arranged
as ports P0
0
to P8
7
. Each port bit can be configured
as input or output. To set the I/O port bit direction,
write a “1” to the corresponding direction register bit
to select output mode, or write a “0” to the direction
register bit to select input mode.
At reset, all of the direction registers are initialized to
00
16
, setting all of the I/O ports to input mode.
If data is written to a pin and then read from that pin
while it is in output mode, the data read is the value of
the port latch rather than the value of the pin itself.
Therefore, if an external load changes the value of an
output pin, the intended output value will still be read
correctly. Pins set to input mode are floating (pro-
vided that the pull up resistors are not being used) to
ensure that the value input to such a pin can be read
accurately. In the case when data is written to a pin
configured as an input, the data is written only to the
port latch; the pin itself remains floating.
Most of the I/O Ports are multiplexed with secondary
functions. When a GPI/O is multiplexed with a sec-
ond function, the control signal from the peripheral
overrides the direction register. The multiplexing is
briefly described below. The second function signals
to and from the I/O ports are described in detail in
their respective block’s description.
1.14.1.1 Ports P0, P1, and P3
Ports P0 and P1 act as the address bus (AB
0
-AB
15
)
in Microprocessor and Memory Expansion modes.
Bits 0 and 3-7 of Port P3 acts as control signals in
Microprocessor and Memory Expansion modes.
1.14.1.2 Port P2
Port P2 is an 8-bit general purpose I/O port when in
single chip mode. In this mode, the port has key-on
wake up circuitry which can be used to restart the
chip externally from a WIT or STP low power mode.
This port also acts as the data bus during micropro-
cessor and memory expansion modes. Port P2 input
level can be set to reduced VIHL level or CMOS level
by bit 6 of the port control register (PTC).
Fig. 1.15. Ports P0, P1, P2, P3 Block Diagram
Ports P0, P1, P3
Port P2
Direction Register
Data Bus
Port Latch
相關(guān)PDF資料
PDF描述
7641 7641 Group Datasheet Datasheet 2145K/MAR.26.02
7643 IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
765-11-(SERIES) Analog IC
765-11-20K Analog IC
765-11-25A Analog IC
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