參數(shù)資料
型號: 71V67703S75BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁數(shù): 23/23頁
文件大?。?/td> 515K
代理商: 71V67703S75BQ
6.42
9
IDT71V67703, IDT71V67903, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Flow-Through Outputs, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
1
2
3
4
20 30 50
100
200
tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5309 drw 05
,
VDDQ/2
50
I/O
Z0 =50
5309 drw 03
,
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
___
5 A
|ILI|
LBO Input Leakage Current(1)
VDD = Max., VIN = 0V to VDD
___
30
A
|ILO|
Output Leakage Current
VOUT = 0V to VCC
___
5 A
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
5309 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
(VDDQ = 3.3V/2.5V)
NOTE:
1. The
LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ in will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while
ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l
Ind
Com'l
Ind
Com'l
Ind
IDD
Operating Power Supply Current
Device Se lected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
265
285
210
230
190
210
mA
ISB1
CMOS Standby Power Supply Current Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
50
70
50
70
50
70
mA
ISB2
Clock Running Power Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX (2,.3)
145
165
140
160
135
155
mA
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, VDD = Max.
50
70
50
70
50
70
mA
5309 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 3V
2ns
1.5V
See Figure 1
5309 tbl 10
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