參數(shù)資料
型號(hào): 71V67703S75BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 36 CACHE SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FBGA-165
文件頁數(shù): 1/23頁
文件大?。?/td> 515K
代理商: 71V67703S75BQ
DECEMBER 2003
DSC-5309/05
1
2002 Integrated Device Technology, Inc.
Features
x
256K x 36, 512K x 18 memory configurations
x
Supports fast access times:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
x
LBO
LBO input selects interleaved or linear burst mode
x
Self-timed write cycle with global write control (
GW
GW), byte write
enable (
BWE
BWE), and byte writes (BW
BW
BWx)
x
3.3V core power supply
x
Power down controlled by ZZ input
x
3.3V I/O supply (VDDQ)
x
Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS0,
CS1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
N/A
VSS
Ground
Supply
N/A
5309 tbl 01
256K X 36, 512K X 18
3.3VSynchronousSRAMs
3.3V I/O, Burst Counter
Flow-ThroughOutputs,SingleCycleDeselect
IDT71V67703
IDT71V67903
NOTE:
1.
BW3 and BW4 are not applicable for the IDT71V67903.
Description
The IDT71V67703/7903 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,
data, address and control registers. There are no registers in the data
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67703/7903 can provide four cycles of
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (
ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the
LBO input pin.
TheIDT71V67703/7903SRAMsutilizeIDT’slatesthigh-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
FEBRUARY 2009
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