參數(shù)資料
型號(hào)： 71V65703S85BQ
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 256K X 36 ZBT SRAM, 8.5 ns, PBGA165
封裝： 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FPBGA-165
文件頁數(shù)： 6/26頁
文件大?。?/td> 512K
代理商： 71V65703S85BQ
6.42
14
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
Write Operation with Chip Enable Used(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2.
CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2.
CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD
CE1(2)
CEN
BWx
OE
I/O(3)
Comments
n
X
L
H
L
X
?
Deselected.
n+1
X
L
H
L
X
Z
Deselected.
n+2
A0
H
L
X
Z
Address A0 and Control meet setup.
n+3
X
L
H
L
X
L
Q0
Address A0 read out, Deselected.
n+4
A1
H
L
X
Z
Address A1 and Control meet setup.
n+5
X
L
H
L
X
L
Q1
Address A1 read out, Deselected.
n+6
X
L
H
L
X
Z
Deselected.
n+7
A2
H
L
X
Z
Address A2 and Control meet setup.
n+8
X
L
H
L
X
L
Q2
Address A2 read out, Deselected.
n+9
X
L
H
L
X
Z
Deselected.
5298 tbl 19
Cycle
Address
R/
W
ADV
/LD
CE(2)
CEN
BWx
OE
I/O
Comments
n
X
L
H
L
X
?
Deselected.
n+1
X
L
H
L
X
Z
Deselected.
n+2
A0
L
LLL
X
Z
Address A0 and Control meet setup
n+3
X
L
H
L
X
D0
Data D0 Write In, Deselected.
n+4
A1
L
LLL
X
Z
Address A1 and Control meet setup
n+5
X
L
H
L
X
D1
Data D1 Write In, Deselected.
n+6
X
L
H
L
X
Z
Deselected.
n+7
A2
L
LLL
X
Z
Address A2 and Control meet setup
n+8
X
L
H
L
X
D2
Data D2 Write In, Deselected.
n+9
X
L
H
L
X
Z
Deselected.
5298 tbl 20
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