參數(shù)資料
型號: 71V65703S85BQ
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 36 ZBT SRAM, 8.5 ns, PBGA165
封裝: 13 X 15 MM, 1.2 MM HEIGHT, 1 MM PITCH, FPBGA-165
文件頁數(shù): 14/26頁
文件大?。?/td> 512K
代理商: 71V65703S85BQ
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation(1,2,3,4)
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
D
(A
3)
represents
the
input
data
to
the
SRAM
corresponding
to
address
A
3etc.
2.
CE
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
When
either
one
of
the
Chip
enables
(
CE
1,
CE2,
CE
2)
is
sampled
inactive
at
the
rising
clock
edge,
a
deselect
cycle
is
initiated.
The
data-bus
tri-states
one
cycle
after
the
init
iation
of
the
deselect
cycle.
This
allows
for
any
pending
data
transfers
(reads
or
writes)
to
be
completed.
4.
Individual
Byte
Write
signals
(
BW
x)
must
be
valid
on
all
write
and
burst-write
cycles.
A
write
cycle
is
initiated
when
R/
W
signal
is
sampled
LOW.
The
byte
write
information
comes
in
one
cycle
before
the
actual
data
is
presented
to
the
SRAM.
R
/W
A
1
C
L
K
A
D
V
/L
D
A
D
R
E
S
C
E
1
,
C
E
2
(2)
O
E
D
A
T
A
O
U
T
Q
(A
1
)
Q
(A
2
)
Q
(A
4
)
tC
LZ
Q
(A
5
)
tC
D
tC
H
Z
tC
D
C
D
(A
3
)
tS
D
tH
D
tC
H
tC
L
tC
Y
C
tH
C
tS
C
A
5
A
3
tS
B
D
A
T
A
IN
tH
E
tS
E
A
2
tH
A
tS
A
4
tH
W
tS
W
tH
B
C
E
N
tH
A
D
V
tS
A
D
V
5
298
dr
w
10
B
W
1
-
B
W
4
B
(A
3)
,
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