參數(shù)資料
型號: 71V65703S75BGG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝: 14 X 22 MM, GREEN, PLASTIC, MS-026AA, BGA-119
文件頁數(shù): 7/26頁
文件大小: 972K
代理商: 71V65703S75BGG
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V±5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V±5%)
NOTE:
1. The
LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
___
5 A
|ILI|
LBO Input Leakage Current(1)
VDD = Max., VIN = 0V to VDD
___
30
A
|ILO|
Output Leakage Current
VOUT = 0V to VCC
___
5 A
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
5298 tbl 21
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l
Ind
Com'l
Ind
Com'l
Ind
IDD
Operating Power
Supply Current
Device Selected, Outputs Open,
ADV/
LD = X, VDD = Max.,
VIN > VIH or < VIL, f = fMAX(2)
275
295
250
60
225
60
mA
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = 0(2,3)
40
60
40
60
40
60
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open,
VDD = Max., VIN > VHD or < VLD,
f = fMAX(2,3)
105
125
100
120
95
115
mA
ISB3
Idle Power
Supply Current
Device Selected, Outputs Open,
CEN > VIH, VDD = Max.,
VIN > VHD or < VLD, f = fMAX(2,3)
40
60
40
60
40
60
mA
IZZ
Full Sleep Mode
Supply Current
Device Selected, Outputs Open,
CEN < VIL, VDD = Max., ZZ > VHD
VIN > VHD or < VLD, f = fMAX(2,3)
40
60
40
60
40
60
mA
5298 tbl 22
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
0 to 3V
2ns
1.5V
Figure 1
5298 tbl 23
VDDQ/2
50
I/O
Z0 =50
5298 drw 04
,
1
2
3
4
20 30 50
100
200
tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5298 drw 05
,
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