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| 型號(hào)： | 71V65703S75BGG |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 256K X 36 ZBT SRAM, 7.5 ns, PBGA119 |
| 封裝： | 14 X 22 MM, GREEN, PLASTIC, MS-026AA, BGA-119 |
| 文件頁(yè)數(shù)： | 26/26頁(yè) |
| 文件大?。?/td> | 972K |
| 代理商： | 71V65703S75BGG |
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6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
9
Interleaved Burst Sequence Table (LBO=VDD)
Partial Truth Table for Writes(1)
Synchronous Truth Table(1)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/
LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/
W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (
CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When
CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the
I/Os remains unchanged.
5. To select the chip requires
CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CEN
R/
W
CE1,CE2(5)
ADV/
LD
BWx
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
(One cycle later)
L
Valid
External
X
LOAD WRITE
D(7)
L
H
L
X
External
X
LOAD READ
Q(7)
L
X
H
Valid
Internal
LOAD WRITE /
BURST WRITE
(Advance burst counter)(2)
D(7)
L
X
H
X
Internal
LOAD READ /
BURST READ
(Advance burst counter)(2)
Q(7)
L
X
H
L
X
DESELECT or STOP(3)
HIZ
L
X
H
X
DESELECT / NOOP
NOOP
HIZ
H
X
SUSPEND
(4)
Previous Value
5298 tbl 08
OPERATION
R/
W
BW1
BW2
BW3(3)
BW4(3)
READ
H
XXX
X
WRITE ALL BYTES
L
WRITE BYTE 1 (I/O[0:7], I/OP1)(2)
LL
H
WRITE BYTE 2 (I/O[8:15], I/OP2)(2)
LH
H
WRITE BYTE 3 (I/O[16:23], I/OP3)(2,3)
LH
H
L
H
WRITE BYTE 4 (I/O[24:31], I/OP4)(2,3)
LH
H
L
NO WRITE
L
HH
5298 tbl 09
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
1
0
1
Second Address
0
1
0
1
0
Third Address
1
0
1
0
1
Fourth Address(1)
111
00
1
0
5298 tbl 10
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相關(guān)代理商/技術(shù)參數(shù) |
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| 71V65703S75BGG8 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V65703S75BQ | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 71V65703S75BQ8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 7.5ns 165-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC SGL 3.3V 9MBIT 256KX36 7.5NS 165FPBGA - Tape and Reel |
| 71V65703S75BQG | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 7.5ns 165-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 7.5ns 165-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC SGL 3.3V 9MBIT 256KX36 7.5NS 165FPBGA - Rail/Tube |
| 71V65703S75BQG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 7.5ns 165-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC SGL 3.3V 9MBIT 256KX36 7.5NS 165FPBGA - Tape and Reel |
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