參數(shù)資料
型號(hào): 71V65703S75BGG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 36 ZBT SRAM, 7.5 ns, PBGA119
封裝: 14 X 22 MM, GREEN, PLASTIC, MS-026AA, BGA-119
文件頁數(shù): 11/26頁
文件大?。?/td> 972K
代理商: 71V65703S75BGG
6.42
IDT71V65703, IDT71V65903, 256K x 36, 512K x 18, 3.3V Synchronous ZBT SRAMs with
3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
19
Timing Waveform of Combined Read and Write Cycles(1,2,3)
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
D
(A
2)
represents
the
input
data
to
the
SRAM
corresponding
to
address
A
2.
2.
CE
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
Individual
Byte
Write
signals
(
BW
x)
must
be
valid
on
all
write
and
burst-write
cycles.
A
write
cycle
is
initiated
when
R/
W
signal
is
sampled
LOW.
The
byte
write
information
comes
in
one
cycle
before
the
actual
data
is
presented
to
the
SRAM.
tH
E
tS
E
R
/W
A
1
A
2
C
LK
C
E
N
A
D
V
/LD
A
D
R
E
S
C
E
1
,
C
E
2
(2)
B
W
1
-
B
W
4
D
A
T
A
O
U
T
Q
(A
3
)
Q
(A
1
)
Q
(A
6
)
Q
(A
7
)
tC
D
R
ea
d
R
ea
d
R
ea
d
R
ea
d
tC
H
Z
52
98
drw
08
W
ri
te
tC
LZ
D
(A
2
)
D
(A
4
)
tC
D
C
D
(A
5
)
W
ri
te
tC
H
tC
L
tC
Y
C
tH
W
tS
W
tH
A
tS
A
4
A
3
tH
C
tS
C
tS
D
tH
D
tH
A
D
V
tS
A
D
V
A
6
A
7
A
8
A
5
A
9
D
A
T
A
IN
tH
B
tS
B
W
ri
te
D
(A
8
)
W
rite
B
(A
2)
B
(A
4
)
B
(A
5
)
B
(A
8
)
O
E
,
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