- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68811 > 71M6542F-IGTR/F (MAXIM INTEGRATED PRODUCTS INC) SPECIALTY ANALOG CIRCUIT, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | 71M6542F-IGTR/F |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁(yè)數(shù)： | 98/165頁(yè) |
| 文件大?。?/td> | 2208K |
| 代理商： | 71M6542F-IGTR/F |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)當(dāng)前第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)
38
2008–2011 Teridian Semiconductor Corporation
v1.1
UART Control Registers:
The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON
Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice
would be to clear them with a bit operation, but this must be avoided. The hardware implements
bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after
the read, but before the write, its flag is cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except for
a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 19: The S0CON (UART0) Register (SFR 0x98)
Bit
Symbol
Function
S0CON[7]
SM0
The SM0 and SM1 bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
S0CON[6]
SM1
S0CON[5]
SM20
Enables the inter-processor communication feature.
S0CON[4]
REN0
If set, enables serial reception. Cleared by software to disable reception.
S0CON[3]
TB80
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the
MPU, depending on the function it performs (parity check, multiprocessor
communication etc.)
S0CON[2]
RB80
In Modes 2 and 3 it is the 9
th data bit received. In Mode 1, SM20 is 0,
RB80 is the stop bit. In mode 0, this bit is not used. Must be cleared by
software.
S0CON[1]
TI0
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
S0CON[0]
RI0
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
Table 20: The S1CON (UART1) Register (SFR 0x9B)
Bit
Symbol
Function
S1CON[7]
SM
Sets the baud rate and mode for UART1.
SM
Mode
Description
Baud Rate
0
A
9-bit UART
variable
1
B
8-bit UART
variable
S1CON[5]
SM21
Enables the inter-processor communication feature.
S1CON[4]
REN1
If set, enables serial reception. Cleared by software to disable reception.
S1CON[3]
TB81
The 9
th transmitted data bit in Mode A. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
S1CON[2]
RB81
In Modes A and B, it is the 9
th data bit received. In Mode B, if SM21 is 0,
RB81 is the stop bit. Must be cleared by software
S1CON[1]
TI1
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software (see Caution above).
S1CON[0]
RI1
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software (see Caution above).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 71M6541D-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 71M6542G-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 71M6541G-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 71M6541F-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 71M6543F-IGT/F | SPECIALTY ANALOG CIRCUIT, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 71M6542FT-IGT/F | 制造商:Maxim Integrated Products 功能描述:1-PHASE SOC 128KB WITH PREC TEMP SENSOR - Rail/Tube |
| 71M6542FT-IGTR/F | 制造商:Maxim Integrated Products 功能描述:1-PHASE SOC, 64KB FLASH, PRES TEMP SENSOR - Tape and Reel |
| 71M6542G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:71M6541D/71M6541F/71M6541G/71M6542F/71M6542G 是 TeridianTM 的第4 代高集成度單相電表SoC |
| 71M6542G-IGT/F | 功能描述:計(jì)量片上系統(tǒng) - SoC 1-Phase Metering SOC with 128KB Flash RoHS:否 制造商:Maxim Integrated 核心:80515 MPU 處理器系列:71M6511 類型:Metering SoC 最大時(shí)鐘頻率:70 Hz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:7 KB 接口類型:UART 可編程輸入/輸出端數(shù)量:12 片上 ADC: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:LQFP-64 封裝:Reel |
| 71M6542G-IGTR/F | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。