參數(shù)資料
型號： 71M6542F-IGTR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 49/165頁
文件大?。?/td> 2208K
代理商： 71M6542F-IGTR/F
142
2008–2011 Teridian Semiconductor Corporation
v1.1
6.4.5
Supply Current
The supply currents provided in Table 100 below include only the current consumed by the 71M654x.
Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x01 remote sensor.
Table 100: Supply Current Performance Specifications
Parameter
Condition
Min
Typ
Max
Unit
I1:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Single-phase: 2 Currents, 1 Voltage
V3P3A = V3P3SYS = 3.3 V,
MPU_DIV [2:0]= 3 (614 kHz MPU clock),
No Flash memory write,
RTM_E=0, PRE_E=0, CE_E=1, ADC_E=1,
ADC_DIV=1, MUX_DIV[3:0]=3,
FIR_LEN[1:0]=1, PLL_FAST=1
5.5
6.7
mA
I1a:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Same as I1, except PLL_FAST=0
2.6
3.5
mA
I1b:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Same as I1, except PRE_E = 1
5.7
6.9
mA
I1c:
V3P3A + V3P3SYS current,
Half-Speed (ADC_DIV=1)
(see note 1)
Same as I1, except PLL_FAST = 0 and
PRE_E = 1
2.6
3.6
mA
I2:
V3P3A + V3P3SYS dynamic
current
Same as I1, except with variation of
MPU_DIV[2:0].
4.3
I
-
I
3
MPU_DIV
0
MPU_DIV
=
0.4
0.6
mA/
MHz
VBAT current
I3: MSN Mode
I4: BRN Mode
I5: LCD Mode (ext. VLCD)
I6: LCD Mode (boost, DAC)
Note 1
I7: LCD Mode (DAC)
Note 1
I8: LCD Mode (VBAT)
Note 1
I9: SLP Mode
CE_E=0
LCD_VMODE[1:0]=3, also see note 2
LCD_VMODE[1:0]=2, also see note 3
LCD_VMODE[1:0]=1, also see note 3
LCD_VMODE[1:0]=0, also see note 3
SLP Mode
-300
0
2.4
0.4
24
3.0
1.1
0
300
3.2
108
36
11
3.4
+300
nA
mA
nA
A
nA
VBAT_RTC current
I10: MSN
I11: BRN
I12: LCD Mode
I13: SLP Mode
I14: SLP Mode (see note 1)
LCD_VMODE[1:0]=2, also see note 2
TA
≤ 25 °C
TA = 85 °C
-300
0
240
1.8
0.7
1.5
300
320
4.1
1.7
3.2
nA
A
I15:
V3P3A + V3P3SYS current,
Write Flash with ICE
Same as I1, except write Flash at maximum rate,
CE_E=0, ADC_E=0.
7.1
8.7
mA
Notes:
1.
Guaranteed by design; not production tested.
2.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 1, LCD_BLANK=0, LCD_ON=1.
3.
LCD_DAC[4:0]=5 (2.9V), LCD_CLK[1:0]=2, LCD_MODE[2:0]=6, all LCD_MAPn bits = 0.
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