參數(shù)資料
型號(hào)： 70V3319S166BFG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 256K X 18 DUAL-PORT SRAM, 3.6 ns, CBGA208
封裝： 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208
文件頁(yè)數(shù)： 7/23頁(yè)
文件大小： 222K
代理商： 70V3319S166BFG
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
15
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
5623 drw 12
Qn
Qn + 3
DATAOUT
CE1
UB, LB
tCD2
tCKHZ
tCKLZ
tCD2
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
tCH2
tCL2
tCYC2
READ
NOP
READ
tSD tHD
(3)
(1)
tSW tHW
WRITE
(4)
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
DATAIN
Dn + 3
Dn + 2
CE0
CLK
5623 drw 13
DATAOUT
Qn
Qn + 4
CE1
UB, LB
OE
tCH2
tCL2
tCYC2
tCKLZ
tCD2
tOHZ
tCD2
tSD
tHD
READ
WRITE
READ
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
(3)
(1)
tSW tHW
(4)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
70V3319S166BFG8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 208FPBGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
70V3319S166PRF 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
70V3319S166PRF8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 128TQFP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
70V3319S166PRFG 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
70V3319S166PRFG8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 128TQFP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM
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