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參數(shù)資料
| 型號(hào)： | 70V3319S166BFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 3.6 ns, CBGA208 |
| 封裝： | 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208 |
| 文件頁(yè)數(shù)： | 6/23頁(yè) |
| 文件大?。?/td> | 222K |
| 代理商： | 70V3319S166BFG |
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6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
14
CLK"A"
R/
W"A"
ADDRESS"A"
DATAIN"A"
CLK"B"
R/
W"B"
ADDRESS"B"
DATAOUT"B"
tSW
tHW
tSA
tHA
tSD
tHD
tSW
tHW
tSA
tHA
tCO(3)
tCD2
NO
MATCH
VALID
NO
MATCH
VALID
5623 drw 10
tDC
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
NOTES:
1.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2.
OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
DATAIN "A"
CLK "B"
R/
W "B"
ADDRESS "A"
R/
W "A"
CLK "A"
ADDRESS "B"
NO
MATCH
NO
MATCH
VALID
tCD1
tDC
DATAOUT "B"
5623 drw 11
VALID
tSW
tHW
tSA
tHA
tSD
tHD
tHW
tCD1
tCO
tDC
tSA
tSW
tHA
(3)
NOTES:
1.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2.
OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 70V3319S166BFG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 208FPBGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
| 70V3319S166PRF | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V3319S166PRF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 128TQFP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
| 70V3319S166PRFG | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V3319S166PRFG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 128TQFP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
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