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參數(shù)資料
| 型號： | 70824L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 25 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 70824L25PF |
16
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Read STRT/EOB Flag Timing - Sequential Port
CNTEN
(2)
tOLZ
tOHZ
D1
D2
SSTRT1/2
SR/
W
SCE
SOE
SCLK
tCYC
tCH
tCL
tEH
tES
tEH
tES
(4)
(1)
Dx
HIGH IMPEDANCE
tWS
tWH
tWS
tWH
tCD
tSOE
tWS
tWH
tWS
tWH
(2)
tDS
tDH
D0
tCKLZ
(3)
(5)
EOB1/2
tEB
SI/OIN
SI/OOUT
3099 drw19
D3
Sequential Port: Write, Pointer Load, Burst Read
NOTES:
1. If
SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If
CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following
SLD even if CNTEN is LOW.
NOTES: (Also used in Figure "Read
STRT/EOB Flag Timing")
1. If
SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If
CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3.
SOE will control the output and should be HIGH on power-up. If SCE = VIL and is clocked in while SR/W = VIH, the data addressed will be read out within that
cycle. If
SCE = VIL and is clocked in while SR/W = VIL, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
contention and permit a write on this cycle.
4. Unlike
SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/
W = VIL, data would be written to D0 again since CNTEN = VIH.
6.
SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
tCYC
D1
D0
tCH
tCL
tDS
tDH
tOHZ
tEH
tES
tEH
tES
(1)
(3)
A0
Dx
HIGH IMPEDANCE
tWS
tWH
tWS
tWH
tOLZ
tCKLZ
tWS
tWH
(2)
tDS
tDH
(2)
SLD
CNTEN
SR/
W
SCE
SOE
SCLK
SI/OIN
SI/OOUT
3099 drw 18
tSD
tSOP
tWS
D2
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