參數(shù)資料
型號： 70824L25PF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 4K X 16 STANDARD SRAM, 25 ns, PQFP80
封裝： TQFP-80
文件頁數(shù)： 18/21頁
文件大?。?/td> 191K
代理商： 70824L25PF
6
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
DataRetentionPowerDown/UpWaveform(RandomandSequentialPort)(1,2)
Figure 3.
Lumped Capacitance Load Typical Derating Curve
AC Test Conditions
Figure 1. AC Output Test Load
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ, tBHZ,
tOHZ,tWHZ, tCKHZ, and tCKLZ)
(*Including scope and jig.)
NOTES :
1.
SCE is synchronized to the sequential clock input.
2.
CMD > VCC - 0.2V.
DATA RETENTION MODE
VCC
CE
3099 drw 04
4.5V
tCDR
tR
VDR
VIH
4.5V
VDR
2V
≥
SCLK
SCE
VIH
ICC
ISB
tPD
ISB
tPU
3099 drw 06
893
30pF
347
5V
DATAOUT
893
5pF*
347
5V
DATAOUT
3099 drw 05
,
1
2
3
4
5
6
7
8
20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
capacitance.
3099 drw 07
tAA/tCD/tEB
(Typical, ns)
-1
-2
-3
,
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
Figures 1,2 and 3
3099 tbl 10
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