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參數(shù)資料
| 型號： | 70824L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 25 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 191K |
| 代理商： | 70824L25PF |
6.42
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
19
Sequential Counter Enable Cycle After Reset, Write Cycle(1,4,6)
Sequential Counter Enable Cycle After Reset, Read Cycle(1,4)
NOTES:
1. 'D0' represents data input for Address = 0, 'D1' represents data input for Address = 1, etc.
2. If
CNTEN = VIL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a tCD after the SR/
W = VIH is clocked. The RST sets SR/W = LOW internally and therefore disables the output until the next clock.
4.
SCE = VIL throughout all cycles.
5. If
CNTEN=VIL then 'D1' would be clocked out (read) at this point.
6. SR/
W = VIL.
RST
CNTEN
SCLK
(2)
D0
SI/OIN
3099 drw 23
D1
D2
D3
D4
RST
CNTEN
SCLK
(5)
SI/OOUT
3099 drw 24
D0
D2
D1
D3
SR/
W
(3)
(5)
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