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參數(shù)資料
| 型號： | 70824L25PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 4K X 16 STANDARD SRAM, 25 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 70824L25PF |
20
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
Military and Commercial Temperature Ranges
Random Access Port - Reset Timing
Random Access Port Restart Timing of Sequential Port(1)
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when
CMD = VIL and CE = VIH. The device is in the Buffer Command Mode (see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/
W or SCE from being LOW for tWERS and tRSRC periods or SCLK must not toggle from LOW-to-HIGH until after tRSRC.
tRSPW
RST
R/
W,SR/WCMD
or (
UB + LB)
tRSRC
tWERS
EOB(1 or 2)
Flag Valid
tRSFV
3099 drw 25
(4)
tFS
SCLK
R/
W
(Internal Signal)
2-5ns
6-7ns
0.5 x tCYC
3099 drw 26
CLR
Block
(3)
(2)
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| 70824L35PF | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Async Dual 5V 64K-Bit 4K x 16 35ns 80-Pin TQFP Tray |
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