The VCCPD power pins must be connected to a 2.5 V, 3.0 V, or 3.3 V power supply. Using these power pins
to supply the pre-driver power to the output buffers increases the performance of the output pins.
If the input signal is 3.0 V or 3.3 V, Altera recommends that you use a clamping diode on the I/O
pins.
Note:
Related Information
I/O Design Guidelines for Cyclone V Devices
There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
Each I/O bank can simultaneously support multiple I/O standards. The following sections provide guidelines
for mixing non-voltage-referenced and voltage-referenced I/O standards in the devices.
Non-Voltage-Referenced I/O Standards
Each Cyclone V I/O bank has its own VCCIO pins and supports only one VCCIO of 1.2, 1.25, 1.35, 1.5, 1.8,
2.5, 3.0, or 3.3 V. An I/O bank can simultaneously support any number of input signals with different I/O
standard assignments if the I/O standards support the VCCIO level of the I/O bank.
For output signals, a single I/O bank supports non-voltage-referenced output signals that drive at the same
voltage as VCCIO. Because an I/O bank can only have one VCCIO value, it can only drive out the value for
non-voltage-referenced signals.
For example, an I/O bank with a 2.5 V VCCIO setting can support 2.5 V standard inputs and outputs, and
3.0 V LVCMOS inputs only.
Related Information
Voltage-Referenced I/O Standards
To accommodate voltage-referenced I/O standards:
Each Cyclone V I/O bank contains a dedicated VREF pin.
Each bank can have only a single VCCIO voltage level and a single voltage reference (VREF) level.
An I/O bank featuring single-ended or differential standards can support different voltage-referenced
standards if the VCCIO and VREF are the same levels.
For performance reasons, voltage-referenced input standards use their own VCCPD level as the power source.
This feature allows you to place voltage-referenced input signals in an I/O bank with a VCCIO of 2.5 V or
below. For example, you can place HSTL-15 input pins in an I/O bank with 2.5 V VCCIO. However, the
voltage-referenced input with RT OCT enabled requires the VCCIO of the I/O bank to match the voltage of
the input standard. RT OCT cannot be supported for the HSTL-15 I/O standard when VCCIO is 2.5 V.
Voltage-referenced bidirectional and output signals must be the same as the VCCIO voltage of the I/O bank.
For example, you can place only SSTL-2 output pins in an I/O bank with a 2.5 V VCCIO.
Altera Corporation
I/O Features in Cyclone V Devices
5-11
I/O Design Guidelines for Cyclone V Devices
CV-52005
2014.01.10