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參數(shù)資料
| 型號： | 5962F0721401VZC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026VFB, QFP-128 |
| 文件頁數(shù)： | 39/48頁 |
| 文件大?。?/td> | 1421K |
| 代理商： | 5962F0721401VZC |
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2.11 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails.
For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the AD-
C08D1520. Such practice may lead to conversion inaccura-
cies and even to device damage.
Driving the V
BG pin to change the reference voltage. As
mentioned in 2.2 THE REFERENCE VOLTAGE, the refer-
ence voltage is intended to be fixed to provide one of two
different full-scale values (650 mV
P-P and 870 mVP-P). Over
driving this pin will not change the full scale value, but can be
used to change the LVDS common mode voltage from 0.8V
to 1.2V by tying the V
BG pin to VA.
Driving the clock input with an excessively high level
signal.
The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
Inadequate input clock levels.
As described in 2.4 THE
CLOCK INPUTS, insufficient input clock levels can result in
poor performance. Excessive input clock levels could result
in the introduction of an input offset.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace.
This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Failure to provide adequate heat removal.
As described in
2.7.2 Thermal Management, it is important to provide ade-
quate heat removal to ensure device reliability. This can be
done either with adequate air flow or the use of a simple heat
sink built into the board. The backside pad should be ground-
ed for best performance.
www.national.com
44
ADC08D1520QML
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| 5962-0721401VZC | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
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