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參數(shù)資料
| 型號(hào)： | 5962F0721401VZC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026VFB, QFP-128 |
| 文件頁數(shù)： | 34/48頁 |
| 文件大?。?/td> | 1421K |
| 代理商： | 5962F0721401VZC |
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Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
3
OutV / SCLK
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude
and reduced power consumption. See 1.1.6 The LVDS
Outputs. When the extended control mode is enabled, this
pin functions as the SCLK input which clocks in the serial
data. See 1.2 NON-EXTENDED CONTROL/EXTENDED
CONTROL for details on the extended control mode. See
1.3 THE SERIAL INTERFACE for description of the serial
interface.
29
PDQ
A logic high on the PDQ pin puts only the Q-Channel ADC
into the Power Down mode.
4
OutEdge / DDR /
SDATA
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. See 1.1.5.2 OutEdge and
Demultiplex Control Setting When this pin is connected to
1/2 the supply voltage,V
A/2, DDR clocking is enabled. When
the Extended Control Mode is enabled, this pin functions as
the SDATA input. See 1.2 NON-EXTENDED CONTROL/
EXTENDED CONTROL for details on the Extended Control
Mode. See 1.3 THE SERIAL INTERFACE for description of
the serial interface.
15
DCLK_RST/
DCLK_RST+
DCLK Reset. When single-ended DCLK_RST is selected by
setting pin 52 logic high or to V
A/2, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. See 1.5 MULTIPLE ADC
SYNCHRONIZATION for detailed description. When
differential DCLK_RST is selected by setting pin 52 logic low,
this pin receives the positive polarity of a differential pulse
signal used to reset and synchronize the DCLK outputs of
multiple converters.
26
PD
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
30
CAL
Calibration Cycle Initiate. A minimum t
CAL_L input clock
cycles logic low followed by a minimum of t
CAL_H input clock
cycles high on this pin initiates the calibration sequence. See
2.5.2 Calibration for an overview of calibration and 2.5.2.1
Initiating Calibration for a description of calibration.
14
FSR/DCLK_RST-
Full Scale Range Select, Alternate Extended Control Enable
and DCLK_RST-. This pin has two functions. It can
conditionally control the ADC full-scale voltage, or become
the negative polarity signal of a differential pair in differential
DCLK_RST Mode. If pin 52 and pin 41 are connected at logic
high, this pin can be used to set the full-scale-range. When
used as the FSR pin, a logic low on this pin sets the full-scale
differential input range to a reduced V
IN input level. A logic
high on this pin sets the full-scale differential input range to
Higher V
IN input level. See Converter Electrical
Characteristics. When pin 52 is held at logic low, this pin acts
as the DCLK_RST- pin. When in differential DCLK_RST
Mode, there is no pin-controlled FSR and the full-scale-range
is defaulted to the higher V
IN input level.
www.national.com
4
ADC08D1520QML
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