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參數(shù)資料
| 型號： | 5962F0721401VZC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026VFB, QFP-128 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 1421K |
| 代理商： | 5962F0721401VZC |
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TABLE 4. Extended Control Mode Operation
(Pin 41 Logic Low)
Feature
Extended Control Mode Default State
SDR or DDR Clocking
DDR Clocking
DDR Clock Phase
Data changes with DCLK edge (0° phase)
LVDS Output Amplitude
Normal amplitude
(V
OD)
Full-Scale Range
700 mV nominal for both channels
Input Offset Adjust
No adjustment for either channel
Dual Edge Sampling (DES)
Not enabled
Test Pattern
Not present at output
Resistor Trim Disable
Trim enabled, DCLK not continuously present at output
Selectable Output Demultiplexer
1:2 demultiplex
Second DCLK Output
Not present, pin 79 and 80 function as OR+ and OR-.
Sampling Clock Phase Adjust
No adjustment for fine, intermediate or coarse
1.3 THE SERIAL INTERFACE
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS). Nine write only registers are acces-
sible through this serial interface.
SCS:
This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK
: Serial data input is accepted at the rising edge of this
signal.
SDATA:
Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure
6 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 5.
Refer to the Register Description (1.4 REGISTER DESCRIP-
TION) for information on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
IMPORTANT NOTE:
Do not write to the Serial Interface when
calibrating the ADC. Doing so will impair the performance of
the device until it is re-calibrated correctly. Programming the
serial registers will also reduce dynamic performance of the
ADC for the duration of the register access time.
TABLE 5. Register Addresses
4-Bit Address
Loading Sequence:
A3 loaded after H0, A0 loaded last
A3
A2
A1
A0
Hex
Register Addressed
0
0h
Calibration
0
1
1h
Configuration
0
1
0
2h
I- Ch Offset
0
1
3h
I- Ch Full-Scale
Voltage Adjust
0
1
0
4h
Reserved
0
1
0
1
5h
Reserved
0
1
0
6h
Reserved
0
1
7h
Reserved
1
0
8h
Reserved
1
0
1
9h
Extended
Configuration
1
0
1
0
Ah
Q- Ch Offset
1
0
1
Bh
Q- Ch Full-Scale
Voltage Adjust
1
0
Ch
Reserved
1
0
1
Dh
Reserved
1
0
Eh
Sampling Clock Phase
Fine Adjust
1
Fh
Sample Clock Phase
Intermediate and
Coarse Adjust
33
www.national.com
ADC08D1520QML
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