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參數(shù)資料
| 型號： | 5962F0721401VZC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP128 |
| 封裝： | CERAMIC, MS-026VFB, QFP-128 |
| 文件頁數(shù)： | 44/48頁 |
| 文件大?。?/td> | 1421K |
| 代理商： | 5962F0721401VZC |
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Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
127
DES / SCS
Dual Edge Sampling and Serial Interface Chip Select. With
pin 41 logic low, the device is in Extended Control Mode and
this pin is the enable pin for the Serial Interface . When in
Non-Extended Control Mode and this pin is connected to
V
A/2, DES Mode is selected where the I- Channel input is
sampled at twice the input clock rate and the Q- Channel
input is ignored. See 1.1.5.1 Dual-Edge Sampling. When in
Non-Extended Controll Mode and DES is not desired, this
pin should be tied to V
A.
18
19
CLK+
CLK-
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See 1.1.2 Acquiring
CLOCK INPUTS for an overview of the clock inputs.
10
11
.22
23
V
INI
V
INI+
V
INQ+
V
INQ
Analog signal inputs to the ADC. These differential input
signals must be a.c. coupled to these pins. The differential
full-scale input range is programmable using the FSR pin 14
in Non-Extended Control Mode and the Input Full-Scale
Voltage Adjust register in the Extended Control Mode. Refer
to the V
IN specification in the Converter Electrical
Characteristics for the full-scale input range in the Non-
Extended Control Mode. Refer to 1.4 REGISTER
DESCRIPTION for the full-scale input range in the Extended
Control Mode.
31
V
BG
Bandgap output voltage. This pin is capable of sourcing or
sinking 100
μA and can drive a load up to 80 pF.
126
CalRun
Calibration Running indication. This pin is at a logic high
when calibration is running.
32
R
EXT
External bias resistor connection. Nominal value is 3.3 k
(±0.1%) to ground. See 1.1.1 Calibration.
5
www.national.com
ADC08D1520QML
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