參數(shù)資料
型號(hào)： 5962-0520601VZC
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： PROPRIETARY METHOD ADC, CQFP128
封裝： CERAMIC, QFP-128
文件頁(yè)數(shù)： 38/42頁(yè)
文件大小： 1310K
代理商： 5962-0520601VZC
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
18
19
CLK+
CLK-
LVDS Clock input pins for the ADC. The differential clock signal
must be a.c. coupled to these pins. The input signal is sampled on
the falling edge of CLK+. See Section 1.1.2 for a description of
acquiring the input and Section 2.4 for an overview of the clock
inputs.
11
10
.
22
23
V
INI+
V
INI
.
V
INQ+
V
INQ
Analog signal inputs to the ADC. The differential full-scale input
range is 650 mV
P-P when the FSR pin is low, or 870 mVP-P when
the FSR pin is high.
7
V
CMO
Common Mode Voltage. The voltage output at this pin is required
to be the common mode input voltage at V
IN+ and VIN when d.c.
coupling is used. This pin should be grounded when a.c. coupling
is used at the analog inputs. This pin is capable of sourcing or
sinking 100
μA. See Section 2.3.
31
V
BG
Bandgap output voltage capable of 100
μA source/sink.
126
CalRun
Calibration Running indication. This pin is at a logic high when
calibration is running.
32
R
EXT
External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.
34
35
Tdiode_P
Tdiode_N
Temperature Diode Positive (Anode) and Negative (Cathode) for
die temperature measurements. See Section 2.7.2.
5
www.national.com
ADC08D1000QML
相關(guān)PDF資料
PDF描述
5962-0520601VZX PROPRIETARY METHOD ADC, CQFP128
5962-0520601VZC PROPRIETARY METHOD ADC, CQFP128
5962F0520601VZC PROPRIETARY METHOD ADC, CQFP128
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