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參數(shù)資料
| 型號： | 5962-0520601VZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 33/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962-0520601VZC |
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Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
2.10 USING THE SERIAL INTERFACE
The ADC08D1000 may be operated in the non-extended con-
trol (non-Serial Interface) mode or in the extended control
4, 14 and 127 in the non-extended control mode and the ex-
tended control mode, respectively.
2.10.1 Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial
Interface is not active and all controllable functions are con-
trolled with various pin settings. That is, the full-scale range
and input coupling (a.c. or d.c.) are controlled with pin set-
tings. The non-extended control mode is used by setting pin
14 high or low, as opposed to letting it float. Table 6 indicates
the pin functions of the ADC08D1000 in the non-extended
control mode.
TABLE 6. Non-Extended Control Mode Operation (Pin 14
High or Low)
Pin
Low
High
Floating
3
0.50 V
P-P
Output
0.70 V
P-P
Output
n/a
4
OutEdge =
Neg
OutEdge =
Pos
DDR
127
CalDly Low
CalDly High
DES
14
650 mV
P-P
input range
870 mV
P-P
input range
Extended
Control Mode
Pin 3 can be either high or low in the non-extended control
mode. Pin 14 must not be left floating to select this mode. See
Section 1.2 for more information.
Pin 4 can be high or low or can be left floating in the non-
extended control mode. In the non-extended control mode,
pin 4 high or low defines the edge at which the output data
transitions. See Section 2.5.3 for more information. If this pin
is floating, the output clock (DCLK) is a DDR (Double Data
Rate) clock (see Section 1.1.5.3) and the output edge syn-
chronization is irrelevant since data is clocked out on both
DCLK edges.
Pin 127, if it is high or low in the non-extended control mode,
sets the calibration delay. If pin 127 is floating, the calibration
delay is the same as it would be with this pin low and the
converter performs dual edge sampling (DES).
TABLE 7. Extended Control Mode Operation (Pin 14
Floating)
Pin
Function
3
SCLK (Serial Clock)
4
SDATA (Serial Data)
127
SCS (Serial Interface Chip Select)
2.11 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails.
For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the AD-
C08D1000. Such practice may lead to conversion inaccura-
cies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode.
As discussed in sections 1.1.4 and 2.3, the
Input common mode voltage must remain within 50 mV of the
V
CMO output , which has a variability with temperature that
must also be tracked. Distortion performance will be degrad-
ed if the input common mode voltage is more than 50 mV from
V
CMO .
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC08D1000 as many high speed amplifiers will have
higher distortion than will the ADC08D1000, resulting in over-
all system performance degradation.
Driving the V
BG pin to change the reference voltage. As
mentioned in Section 2.2, the reference voltage is intended to
be fixed to provide one of two different full-scale values (650
mV
P-P and 870 mVP-P). Over driving this pin will not change
the full scale value, but can be used to change the LVDS
common mode voltage from 0.8V to 1.2V by tying the V
BG pin
to V
A.
Driving the clock input with an excessively high level
signal.
The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
Inadequate input clock levels.
As described in Section 2.4,
insufficient input clock levels can result in poor performance.
Excessive input clock levels could result in the introduction of
an input offset.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace.
This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Failure to provide adequate heat removal.
As described in
Section 2.7.2, it is important to provide adequate heat removal
to ensure device reliability. This can either be done with ad-
equate air flow or the use of a simple heat sink built into the
board. The backside pad should be grounded for best perfor-
mance.
39
www.national.com
ADC08D1000QML
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