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參數(shù)資料
| 型號： | 5962-0520601VZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 31/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962-0520601VZC |
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2.5.6 Power Down Feature
The Power Down pins (PD and PDQ) allow the ADC08D1000
to be entirely powered down (PD) or the "Q" channel to be
powered down and the "I" channel to remain active. See Sec-
tion 1.1.7 for details on the power down feature.
The digital data (+/-) output pins are put into a high impedance
state when the PD pin for the respective channel is high. Upon
return to normal operation, the pipeline will contain meaning-
less information and must be flushed.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state.
2.6 THE DIGITAL OUTPUTS
The ADC08D1000 demultiplexes the output data of each of
the two ADCs on the die onto two LVDS output buses (total
of four buses, two for each ADC). For each of the two con-
verters, the results of successive conversions started on the
odd falling edges of the CLK+ pin are available on one of the
two LVDS buses, while the results of conversions started on
the even falling edges of the CLK+ pin are available on the
other LVDS bus. This means that, the word rate at each LVDS
bus is 1/2 the ADC08D1000 input clock rate and the two bus-
es must be multiplexed to obtain the entire 1 GSPS conver-
sion result.
Since the minimum recommended input clock rate for this
device is 200 MSPS (normal non DES mode), the effective
rate can be reduced to as low as 100 MSPS by using the
results available on just one of the the two LVDS buses and
a 200 MHz input clock, decimating the 200 MSPS data by two.
There is one LVDS output clock pair (DCLK+/-) available for
use to latch the LVDS outputs on all buses. Whether the data
is sent at the rising or falling edge of DCLK is determined by
the sense of the OutEdge pin, as described in Section 2.5.3.
DDR (Double Data Rate) clocking can also be used. In this
mode a word of data is presented with each edge of DCLK,
reducing the DCLK frequency to 1/4 the input clock frequency.
See the Timing Diagram section for details.
The OutV pin is used to set the LVDS differential output levels.
See Section 2.5.4.
The output format is Offset Binary. Accordingly, a full-scale
input level with V
IN+ positive with respect to VIN will produce
an output code of all ones, a full-scale input level with V
IN
positive with respect to V
IN+ will produce an output code of all
zeros and when V
IN+ and VIN are equal, the output code will
vary between codes 127 and 128.
2.7 POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A 33 F
capacitor should be placed within an inch (2.5 cm) of the A/D
converter power pins. A 0.1 F capacitor should be placed as
close as possible to each V
A pin, preferably within one-half
centimeter. Leadless chip capacitors are preferred because
they have low lead inductance.
The V
A and VDR supply pins should be isolated from each
other to prevent any digital noise from being coupled into the
analog portions of the ADC. A ferrite choke, such as the JW
Miller FB20009-3B, is recommended between these supply
lines when a common source is used for them.
As is the case with all high speed converters, the AD-
C08D1000 should be assumed to have little power supply
noise rejection. Any power supply used for digital circuitry in
a system where a lot of digital power is being consumed
should not be used to supply power to the ADC08D1000. The
ADC supplies should be the same supply used for other ana-
log circuitry, if not a dedicated supply.
2.7.1 Supply Voltage
The ADC08D1000 is specified to operate with a supply volt-
age of 1.9V ±0.1V. It is very important to note that, while this
device will function with slightly higher supply voltages, these
higher supply voltages may reduce product lifetime.
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 150 mV, not
even on a transient basis. This can be a problem upon appli-
cation of power and power shut-down. Be sure that the sup-
plies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the AD-
C08D1000QML power pins.
The Absolute Maximum Ratings should be strictly observed,
even during power up and power down. A power supply that
produces a voltage spike at turn-on and/or turn-off of power
can destroy the ADC08D1000. The circuit of Figure 18 will
provide supply overshoot protection.
Many linear regulators will produce output spiking at power-
on unless there is a minimum load provided. Active devices
draw very little current until their supply voltages reach a few
hundred millivolts. The result can be a turn-on spike that can
destroy the ADC08D1000, unless a minimum load is provided
for the supply. The 100
resistor at the regulator output pro-
vides a minimum output current during power-up to ensure
there is no turn-on spiking.
In the circuit of Figure 18, an LM317 linear regulator is satis-
factory if its input supply voltage is 4V to 5V . If a 3.3V supply
is used, an LM1086 linear regulator is recommended.
20180254
FIGURE 18. Non-Spiking Power Supply
The output drivers should have a supply voltage, V
DR, that is
within the range specified in the Operating Ratings table. This
voltage should not exceed the V
A supply voltage.
If the power is applied to the device without an input clock
signal present, the current drawn by the device might be be-
low 200 mA. This is because the ADC08D1000 gets reset
through clocked logic and its initial state is unknown. If the
reset logic comes up in the "on" state, it will cause most of the
analog circuitry to be powered down, resulting in less than
100 mA of current draw. This current is greater than the power
down current because not all of the ADC is powered down.
The device current will be normal after the input clock is es-
tablished.
2.7.2 Thermal Management
The ADC08D1000 is capable of impressive speeds and per-
formance at very low power levels for its speed. However, the
37
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ADC08D1000QML
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