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參數(shù)資料
| 型號： | 5962-0520601VZC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 29/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962-0520601VZC |
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problems, keep the input clock level within the range specified
in the Electrical Characteristics Table.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1000 fea-
tures a duty cycle clock correction circuit which can maintain
performance over temperature even in DES mode. The ADC
will meet its performance specification if the input clock
high and low times are maintained within the range
(30/70% ratio).
High speed, high performance ADCs such as the AD-
C08D1000 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
t
J(MAX) = (VIN(P-P)/VINFSR) x (1/(2
(N+1)
x
π x f
IN))
where t
J(MAX) is the rms total of all jitter sources in seconds,
V
IN(P-P) is the peak-to-peak analog input signal, VINFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and f
IN is the maximum input frequency, in Hertz, to the ADC
analog input.
Note that the maximum jitter described above is the arithmetic
sum of the jitter from all sources, including that in the ADC
input clock, that added by the system to the ADC input clock
and input signals and that added by the ADC itself. Since the
effective jitter added by the ADC is beyond user control, the
best the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
Input clock amplitudes above those specified in the Electrical
Characteristics Table may result in increased input offset volt-
age. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
2.5 CONTROL PINS
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the AD-
C08D1000 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Self Calibration, Calibration
Delay, Output Edge Synchronization choice, LVDS Output
Level choice and a Power Down feature.
2.5.1 Full-Scale Input Range Setting
The input full-scale range can be selected to be either 650
mV
P-P or 870 mVP-P, as selected with the FSR control input
(pin 14) in the Normal Mode of operation. In the Extended
Control Mode, the input full-scale range may be set to be
anywhere from 560 mV
P-P to 840 mVP-P. See Section 2.2 for
more information.
2.5.2 Self Calibration
The ADC08D1000 self-calibration must be run to achieve
specified performance. The calibration procedure is run upon
power-up and can be run any time on command. The cali-
bration procedure is exactly the same whether there is an
input clock present upon power up or if the clock begins some
time after application of power. The CalRun output indicator
is high while a calibration is in progress. Note that DCLK out-
puts are not active during a calibration cycle.
2.5.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
The calibration process will not be performed if the CAL pin
is high at power up. In this case, the calibration cycle will not
begin until the on-command calibration conditions are met.
The ADC08D1000 will function with the CAL pin held high at
power up, but no calibration will be done and performance will
be impaired. A manual calibration, however, may be per-
formed after powering up with the CAL pin high. See On-
Command Calibration Section 2.5.2.2.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
2.5.2.2 On-Command Calibration
On-command calibration may be run at any time in NOR-
MAL (non-DES) mode only. Do not run a calibration while
operating the ADC in Auto DES Mode.
If the ADC is operating in Auto DES mode and a calibration
cycle is required then the controlling application should bring
the ADC into normal (non DES) mode before an On Com-
mand calibration is initiated. Once calibration has completed,
the ADC can be put back into Auto DES mode.
To initiate an on-command calibration, bring the CAL pin high
for a minimum of 640 input clock cycles after it has been low
for a minimum of 640 input clock cycles. Holding the CAL pin
high upon power up will prevent execution of power-on cali-
bration until the CAL pin is low for a minimum of 640 input
clock cycles, then brought high for a minimum of another 640
input clock cycles. The calibration cycle will begin 640 input
clock cycles after the CAL pin is thus brought high. The Cal-
Run signal should be monitored to determine when the cali-
bration cycle has completed.
The minimum 640 input clock cycle sequences are required
to ensure that random noise does not cause a calibration to
begin when it is not desired. As mentioned in section 1.1.1 for
best performance, a self calibration should be performed 20
seconds or more after power up and repeated when the op-
erating temperature changes significantly, according to the
particular system performance requirements. As can be seen
in the following figures ENOB drops slightly with increasing
junction temperature, and a self calibration eliminates the
change. In the first example (see Figure 16), a sample clock
of 1GSPS is used to capture a full-scale 749MHz signal at the
I-channel input as the junction temperature (T
J) is increased
from 65°C to 125°C with no intermediate calibration cycles.
The vertical line at 125°C is the result of an on-command cal-
ibration cycle that essentially eliminates the drop in ENOB. Of
course, calibration cycles can be run more often, at smaller
intervals of temperature change, if system design specifica-
tions require it. In the second example (see Figure 17), the
test method is the same and the I-channel input signal is
249MHz. The variation in ENOB vs. T
J has a smaller range
then the previous example, and is again removed by an on-
command calibration cycle at the maximum test temperature.
35
www.national.com
ADC08D1000QML
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