參數(shù)資料
型號(hào)： 5962-0520601VZC
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： PROPRIETARY METHOD ADC, CQFP128
封裝： CERAMIC, QFP-128
文件頁數(shù)： 25/42頁
文件大?。?/td> 1310K
代理商： 5962-0520601VZC
Bits 15:8
Offset Value. The input offset of the I-Channel
ADC is adjusted linearly and monotonically by
the value in this field. 00h provides a nominal
zero offset, while FFh provides a nominal 45
mV of offset. Thus, each code step provides
0.176 mV of offset.
POR State: 0000 0000 b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Bit 6:0
Must be set to 1b
I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b)
W only (0x807F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Adjust Value
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
Bit 15:7
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
P-P differential value.
0000 0000 0
560mV
P-P
1000 0000 0
Default Value
700mV
P-P
1111 1111 1
840mV
P-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Bits 6:0
Must be set to 1b
Q-Channel Offset
Addr: Ah (1010b)
W only (0x007F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Offset Value
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
Sign
1
Bit 15:8
Offset Value. The input offset of the Q-
Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
POR State: 0000 0000 b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Bit 6:0
Must be set to 1b
Q-Channel Full-Scale Voltage Adjust
Addr: Bh (1011b)
W only (0x807F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Adjust Value
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
Bit 15:7
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mV
P-P differential value.
0000 0000 0
560mV
P-P
1000 0000 0
700mV
P-P
1111 1111 1
840mV
P-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Bits 6:0
Must be set to 1b
DES Enable
Addr: Dh (1101b)
W only (0x3FFF)
D15
D14
D13
D12
D11
D10
D9
D8
DEN
ACP
1
D7
D6
D5
D4
D3
D2
D1
D0
1
31
www.national.com
ADC08D1000QML
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PDF描述
5962-0520601VZX PROPRIETARY METHOD ADC, CQFP128
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