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| 型號(hào)： | 38C1 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | DIODE ZENER SINGLE 200mW 24Vz 0.05mA-Izt 0.05 0.05uA-Ir 18.2 SOD-323 3K/REEL |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 30/59頁(yè) |
| 文件大?。?/td> | 1063K |
| 代理商： | 38C1 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
30
LCD DRIVE CONTROL CIRCUIT
The 38C1 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display register
Segment output enable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 25 segment output pins and 4 common output pins
can be used.
Up to 100 pixels can be controlled for LCD display. When the LCD
enable bit is set to
“
1
”
after data is set in the LCD mode register,
Fig. 29 Structure of segment output enable register and LCD mode register
the segment output enable register and the LCD display register,
the LCD drive control circuit starts reading the display data auto-
matically, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
Table 7. Maximum number of display pixels at each duty ratio
Maximum number of display pixel
25 dots
or 8 segment LCD 3 digits
50 dots
or 8 segment LCD 6 digits
75 dots
or 8 segment LCD 9 digits
100 dots
or 8 segment LCD 12 digits
Duty ratio
1
2
3
4
S
b
0
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2
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6
6
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)
Duty ratio selection bits
b1b0
0 0 : 1 duty (static)
0 1 : 2 duty
1 0 : 3 duty
1 1 : 4 duty
Bias control bit (Note 2)
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used
(Do not write
“
1
”
to this bit.)
LCD circuit divider division ratio selection bits
b6b5
0 0 : Clock input
0 1 : 2 division of Clock input
1 0 : 4 division of Clock input
1 1 : 8 division of Clock input
LCDCK count source selection bit (Note 3)
0 : f(X
CIN
)/32
1 :
φ
SOURCE
/8192
Notes 1:
Set the direction register of the port which is also used as the segment output enabled pin to
“
1
”
.
2:
When
“
1 duty
”
is selected by the duty ratio selection bit, set the bias control bit to
“
1
”
.
3:
LCDCK is a clock for a LCD timing controller.
φ
SOURCE
represents the oscillation frequency of X
IN
input in the middle- and high-speed mode,
built-in ring oscillator in the ring oscillator mode, and sub-clock in the low-speed mode.
b
7
b
0
(Note 1)
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