參數(shù)資料
型號(hào): 38C1
廠商: Mitsubishi Electric Corporation
英文描述: DIODE ZENER SINGLE 200mW 24Vz 0.05mA-Izt 0.05 0.05uA-Ir 18.2 SOD-323 3K/REEL
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 18/59頁(yè)
文件大?。?/td> 1063K
代理商: 38C1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
18
INTERRUPTS
I
nterrupts occur by thirteen sources: five external, seven internal,
and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are
1
and the inter-
rupt disable flag is
0
.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
I
Notes on Interrupts
When the active edge of an external interrupt (INT
0
, INT
1
, CNTR
0
or CNTR
1
) is set or an interrupt source where several interrupt
source is assigned to the same vector address is switched, the
corresponding interrupt request bit may also be set. Therefore,
take following sequence:
(1) Disable the interrupt.
(2) Set the interrupt edge selection register (Timer X control regis-
ter for CNTR0, Timer Y mode register for CNTR
1
).
(3) Clear the set interrupt request bit to
0.
(4) Enable the interrupt.
Notes1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Table 6 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT
0
input
At detection of either rising or
falling edge of INT
1
input
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of CNTR
1
input
At timer 2 underflow
At completion of serial I/O data
transmission or reception
At falling of conjunction of input
level for port P3 (at input mode)
At completion of A-D conversion
At BRK instruction execution
Interrupt Source
Low
FFFC
16
FFFA
16
High
FFFD
16
FFFB
16
Priority
Vector Addresses
(Note 1)
Reset
(Note 2)
INT
0
INT
1
Timer X
Timer Y
Timer 1
Timer 3
CNTR
0
CNTR
1
Timer 2
Serial I/O
Key input
(Key-on wake-up)
A-D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FFF9
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
FFF8
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid at falling)
Valid when A-D interrupt is selected
Non-maskable software interrupt
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