參數(shù)資料
型號(hào)： 29LV800BE
廠商： Fujitsu Limited
英文描述： 8M (1M x 8/512 K x 16) BIT
中文描述： 8米（3米x五百一十二分之八畝× 16）位
文件頁(yè)數(shù)： 26/58頁(yè)
文件大?。?/td> 292K
代理商： 29LV800BE
MBM29LV800TE/BE
60/70/90
25
Byte/Word Configuration
BYTE pin selects byte (8-bit) mode or word (16-bit) mode for MBM29LV800TE/BE devices. When this pin is
driven high, devices operate in word (16-bit) mode. Data is read and programmed at DQ
15
to DQ
0
. When this
pin is driven low, devices operates in byte (8-bit) mode. Under this mode, the DQ
15
/A-
1
pin becomes the lowest
address bit, and DQ
14
to DQ
8
bits are tri-stated. However, the command bus cycle is always an 8-bit operation
and hence commands are written at DQ
7
to DQ
0
and DQ
15
to DQ
8
bits are ignored. Refer to “Timing Diagram
for Word Mode Configuration”, “Timing Diagram for Byte Mode Configuration” and “BYTE Timing Diagram for
Write Operations” in “
I
TIMING DIAGRAM” for the timing diagram.
Data Protection
MBM29LV800TE/BE are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up, devices automatically
reset internal state machine in Read mode. Also, with its control register architecture, alteration of memory
contents only occurs after successful completion of specific multi-bus cycle command sequences.
Devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up and
power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(Min) . If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits are
disabled. Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above V
LKO
(Min) .
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE
=
V
IL
, CE
=
V
IH
, or WE
=
V
IH
. To initiate a write cycle, CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE
=
CE
=
V
IL
and OE
=
V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
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