參數(shù)資料
型號: 28F320S5
廠商: Intel Corp.
英文描述: 3 V、32MB FlashFile Memory(3 V、32M位FlashFile 存儲(chǔ)器)
中文描述: 3伏,32MB的FlashFile內(nèi)存(3伏,32位FlashFile存儲(chǔ)器)
文件頁數(shù): 12/51頁
文件大?。?/td> 320K
代理商: 28F320S5
28F160S5/28F320S5
E
12
PRELIMINARY
Reserved for Future
Implementation
(Subsequent Blocks)
Reserved for Future
Implementation
Block 1 Lock Configuration
Reserved for Future
Implementation
Device Code
Manufacturer Code
Block 0
Block 1
Word
Address
0FFFF
08004
08003
08002
08000
07FFF
00004
00003
00002
00001
00000
A[
20-1
]: 16-Mbit
A[
21-1
]: 32-Mbit
Block 0 Lock Configuration
0609_05
Figure 5. Device Identifier Code Memory Map
3.7
Write
Writing commands to the CUI enables reading of
device data, query, identifier codes, inspection
and clearing of the status register. Additionally,
when V
PP
= V
PPH
, block erasure, programming,
and lock-bit configuration can also be performed.
The Block Erase command requires appropriate
command data and an address within the block
to be erased. The Byte/Word Write command
requires the command and address of the
location to be written. Set Block Lock-Bit
commands require the command and address
within the block to be locked. The Clear Block
Lock-Bits command requires the command and
an address within the device.
The CUI does not occupy an addressable
memory location. It is written when WE#, CE
0
#,
and CE
1
# are active and OE# = V
IH
. The address
and data needed to execute a command are
latched on the rising edge of WE# or CE
X
#
(CE
0
#, CE
1
#), whichever goes high first.
Standard microprocessor write timings are used.
Figure 17 illustrates a write operation.
4.0
COMMAND DEFINITIONS
V
PP
voltage
V
PPLK
enables read operations
from the status register, identifier codes, or
memory blocks. Placing V
PPH
on V
PP
enables
successful block erase, programming, and lock-
bit configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 2 and Table 3
define these commands.
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