參數(shù)資料
型號(hào)： 28F320S5
廠商： Intel Corp.
英文描述： 3 V、32MB FlashFile Memory(3 V、32M位FlashFile 存儲(chǔ)器)
中文描述： 3伏，32MB的FlashFile內(nèi)存（3伏，32位FlashFile存儲(chǔ)器）
文件頁(yè)數(shù)： 10/51頁(yè)
文件大小： 320K
代理商： 28F320S5
28F160S5/28F320S5
E
10
PRELIMINARY
bit configuration can be stored in any block. This
code is copied to and executed from system
RAM during flash memory updates. After
successful completion, reads are again possible
via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read or write data from any other
block. Program suspend allows system software
to suspend a program to read data from any
other flash memory array location.
2.1
Data Protection
Depending on the application, the system
designer may choose to make the V
PP
power
supply switchable or hardwired to V
PPH
. The
device supports either design practice, and
encourages optimization of the processor-
memory interface.
When V
PP
≤
V
PPLK
, memory contents cannot be
altered. When high voltage is applied to V
PP
, the
two-step block erase, program, or lock-bit
configuration
command
protection from unwanted operations. All write
functions are disabled when V
CC
voltage is below
the write lockout voltage V
LKO
or when RP# is at
V
IL
. The device’s block locking capability
provides additional protection from inadvertent
code or data alteration.
sequences
provide
3.0
BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1
Read
Block information, query information, identifier
codes and status registers can be read
independent of the V
PP
voltage.
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component. CE
#, CE
1
# and OE# must be driven
active to obtain data at the outputs. CE
0
# and
CE
1
# are the device selection controls, and,
when both are active, enable the selected
memory device. OE# is the data output (DQ
0
–
DQ
15
) control: When active it drives the selected
memory data onto the I/O bus. WE# must be at
V
and RP# must be at V
IH
. Figure 16 illustrates
a read cycle.
64-Kbyte Block
3FFFFF
3F0000
63
64-Kbyte Block
1FFFFF
1F0000
31
64-Kbyte Block
01FFFF
010000
00FFFF
000000
1
64-Kbyte Block
0
32-Kword Block
1FFFFF
1F0000
63
32-Kword Block
0FFFFF
0F8000
31
32-Kword Block
00FFFF
008000
007FFF
000000
1
32-Kword Block
0
32-Mbit: A[
21-1
]
16-Mbit: A[
20-1
]
32-Mbit: A[
21-0
]
16-Mbit: A[
20-0
]
Byte-Wide (x8) Mode
Word-Wide (x16) Mode
16 Mbit
32 Mbit
0609_04
Figure 4. Memory Map
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