參數(shù)資料
型號(hào): 28F160C2
廠商: Intel Corp.
英文描述: 2.4V Advanced+ Boot Block Flash Memory(2.4V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
中文描述: 2.4V的高級(jí)啟動(dòng)塊閃存(2.4V的高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
文件頁數(shù): 5/56頁
文件大?。?/td> 283K
代理商: 28F160C2
E
1.0
28F800C2, 28F160C2
5
PRELIMINARY
INTRODUCTION
This document contains the specifications for the
2.4 Volt Advanced+ Boot Block flash memory
family. These flash memories add features which
can be used to enhance the security of systems:
instant block locking and a protection register.
Throughout this document, the term
“2.4 V” refers
to the full voltage range 2.4 V–3.0 V (except where
noted otherwise) and “V
PP
=
12 V” refers to 12 V
±5%. Sections 1 and 2 provide an overview of the
flash memory family including applications, pinouts,
pin descriptions and memory organization. Section
3 describes the operation of these products. Finally,
Section 4 contains the operating specifications.
1.1
2.4 Volt Advanced+ Boot Block
Flash Memory Enhancements
The 2.4 Volt Advanced+ Boot Block flash memory
features:
Zero-latency, flexible block locking
128-bit Protection Register
Simple
system
implementation
production programming with 2.4 V in-field
programming
Ultra-low power operation at 2.4 V
Minimum 100,000 block erase cycles
Common Flash Interface for software query of
device specs and features
for
12 V
Table 1. 2.4 Volt Advanced+ Boot Block Feature Summary
Feature
8 Mbit
(1)
, 16 Mbit
Reference
V
CC
Operating Voltage
2.4 V – 3.0 V
Table 8
V
PP
Voltage
Provides complete write protection with
optional 12 V Fast Programming
Table 8
V
CCQ
I/O Voltage
2.4 V– 3.0 V
Bus Width
16-bit
Table 2
Speed (ns)
8/16 Mbit: 100, 120 @ 2.4 V and 90, 110 @ 2.7 V
Section 4.4
Blocking (top or bottom)
8 x 4-Kword parameter
8-Mb: 15 x 32-Kword main
16-Mb: 31 x 32-Kword main
Section 2.2
Appendix E
Operating Temperature
Extended: –40 °C to +85 °C
Table 8
Program/Erase Cycling
100,000 cycles
Table 8
Packages
48-Lead TSOP
48-Ball
μ
BGA* CSP
(1)
Figures 1 and 2
Block Locking
Flexible locking of any block with zero latency
Section 3.3
Protection Register
64-bit unique device number, 64-bit user programmable
Section 3.4
NOTE:
1.
8-Mbit density not available in μBGA* CSP.
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