參數(shù)資料
型號(hào)： 28F160C2
廠商： Intel Corp.
英文描述： 2.4V Advanced+ Boot Block Flash Memory(2.4V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
中文描述： 2.4V的高級(jí)啟動(dòng)塊閃存（2.4V的高級(jí)引導(dǎo)塊閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 22/56頁(yè)
文件大?。?/td> 283K
代理商： 28F160C2
28F800C2, 28F160C2
E
22
PRELIMINARY
V
CC
V
PP
12 V Fast Programming
Absolute Write Protection With V
PP
≤
V
PPLK
System Supply
12 V Supply
10
≤
K
V
CC
V
PP
System Supply
12 V Supply
Low Voltage and 12 V Fast Programming
V
CC
V
PP
System Supply
Prot#
(Logic Signal)
V
CC
V
PP
System Supply
Low-Voltage Programming
Low-Voltage Programming
Absolute Write Protection via Logic Signal
(Note 1)
0645_06
NOTE:
1.
A resistor can be used if the V
CC
supply can sink adequate current based on resistor value. See AP-657 Designing with
the Advanced+ Boot Block Flash Memory Architecturefor details.
Figure 4. Example Power Supply Configurations
3.6
Power Consumption
Intel’s flash devices have a tiered approach to
power savings that can significantly reduce overall
system power consumption. The Automatic Power
Savings (APS) feature reduces power consumption
when the device is selected but idle. If the CE# is
deasserted, the flash enters its standby mode,
where current consumption is even lower. The
combination of these features can minimize
memory power consumption, and therefore, overall
system power consumption.
3.6.1
ACTIVE POWER
(Program/Erase/Read)
With CE# at a logic
-
low level and RP# at a logic
-
high level, the device is in the active mode. Refer to
the DC Characteristic tables for I
CC
current values.
Active power is the largest contributor to overall
system power consumption. Minimizing the active
current could have a profound effect on system
power consumption, especially for battery
-
operated
devices.
3.6.2
AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings provides low
-
power
operation during read mode. After data is read from
the memory array and the address lines are
quiescent, APS circuitry places the device in a
mode where typical current is comparable to I
CCS
.
The flash stays in this static state with outputs valid
until a new location is read.
3.6.3
STANDBY POWER
With CE# at a logic
-
high level (V
IH
) and device in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
are placed in a high
-
impedance state independent
of the status of the OE# signal. If CE# transitions to
a logic
-
high level during erase or program
operations, the device will continue to perform the
operation and consume corresponding active power
until the operation is completed.
相關(guān)PDF資料
PDF描述
28F800C2 2.4V Advanced+ Boot Block Flash Memory(2.4V高級(jí)引導(dǎo)塊閃速存儲(chǔ)器)
28F160S3 3 V FlashFile Memory(3 V FlashFile 存儲(chǔ)器)
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