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參數(shù)資料
| 型號： | 28F128 |
| 廠商： | Intel Corp. |
| 英文描述： | 3 Volt Intel StrataFlash Memory |
| 中文描述： | 3伏特英特爾StrataFlash存儲器 |
| 文件頁數(shù)： | 8/58頁 |
| 文件大?。?/td> | 380K |
| 代理商： | 28F128 |
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28F128J3A, 28F640J3A, 28F320J3A
2
Preliminary
suspended (and programming is inactive), program is suspended, or the device is in reset/power-
down mode. Additionally, the configuration command allows the STS pin to be configured to pulse
on completion of programming and/or block erases.
Three CE pins are used to enable and disable the device. A unique CE logic design (see
Table 2,
“
Chip Enable Truth Table
”
on page 7
) reduces decoder logic typically required for multi-chip
designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip
miniature card or SIMM module.
The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit
mode; address A
0
selects between the low byte and high byte. BYTE# at logic high enables 16-bit
operation; address A
1
becomes the lowest order address and address A
0
is not used (don
’
t care). A
device block diagram is shown in
Figure 1 on page 2
.
When the device is disabled (see
Table 2 on page 7
) and the RP# pin is at V
CC
, the standby mode is
enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes
power consumption and provides write protection during reset. A reset time (t
PHQV
) is required
from RP# switching high until outputs are valid. Likewise, the device has a wake time (t
PHWL
)
from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the
status register is cleared.
3 Volt Intel StrataFlash memory devices are available in two package types. Both 56-lead TSOP
(Thin Small Outline Package) and BGA (Ball Grid Array Package) support all offered densities.
Figure 2
and
Figure 3
show the pinouts.
Figure 1. 3 Volt Intel
StrataFlash
Memory Block Diagram
32-Mbit: Thirty-two
64-Mbit: Sixty-four
128-Mbit: One-hundred
twenty-eight
128-Kbyte Blocks
Input Buffer
O
L
Y-Gating
Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
D
R
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Input Buffer
Output
Buffer
GND
V
BYTE#
V
PEN
CE
0
CE
1
CE
2
WE#
OE#
RP#
Command
User
Interface
32-Mbit: A
0
- A
21
64-Mbit: A
0
-
A
22
128-Mbit: A
0
- A
23
DQ
0
- DQ
15
V
CC
W
Write State
Machine
Multiplexer
Query
STS
V
CCQ
CE
Logic
A
0
- A
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 28F128J3A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Intel StrataFlash Memory |
| 28F128J3A150 | 制造商: 功能描述: 制造商:INTELC 功能描述: 制造商:undefined 功能描述: |
| 28F128J3A-150 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 28F128J3D75 | 制造商: 功能描述: 制造商:Intel 功能描述: |
| 28F128J3FS-12ET | 制造商: 功能描述: 制造商:undefined 功能描述: |
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