參數(shù)資料
型號(hào)： 28F128
廠商： Intel Corp.
英文描述： 3 Volt Intel StrataFlash Memory
中文描述： 3伏特英特爾StrataFlash存儲(chǔ)器
文件頁(yè)數(shù)： 53/58頁(yè)
文件大?。?/td> 380K
代理商： 28F128
28F128J3A, 28F640J3A, 28F320J3A
Preliminary
47
6.6
AC Characteristics
—
Write Operations
(1,2)
NOTES:
CE
X
low is defined as the first edge of CE
0
, CE
1
, or CE
2
that enables the device. CE
X
high is defined at the first edge of CE
0
,
CE
1
, or CE
2
that disables the device (see
Table 2
).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same
as during read-only operations. Refer to
AC Characteristics
–
Read-Only Operations
.
2. A write operation can be initiated and terminated with either CE
X
or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (t
WP
) is defined from CE
X
or WE# going low (whichever goes low first) to CE
X
or WE# going
high (whichever goes high first). Hence, t
WP
= t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
. If CE
X
is driven low 10 ns
before WE# going low, WE# pulse width requirement decreases to t
WP
- 10 ns.
5. Refer to
Table 4
for valid A
IN
and D
IN
for block erase, program, or lock-bit configuration.
6. Write pulse width high (t
WPH
) is defined from CE
X
or WE# going high (whichever goes high first) to CE
X
or
WE# going low (whichever goes low first). Hence, t
WPH
= t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
.
7. For array access, t
AVQV
is required in addition to t
WHGL
for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V
PEN
should be held at V
PENH
until determination of block erase, program, or lock-bit configuration success
(SR.1/3/4/5 = 0).
Versions
Valid for All
Speeds
Unit
#
Symbol
Parameter
Notes
Min
Max
W1
t
PHWL
(t
PHEL
)
RP# High Recovery to WE# (CE
X
) Going Low
3
1
μs
W2
t
ELWL
(t
WLEL
)
CE
X
(WE#) Low to WE# (CE
X
) Going Low
4
0
ns
W3
t
WP
Write Pulse Width
4
70
ns
W4
t
DVWH
(t
DVEH
)
Data Setup to WE# (CE
X
) Going High
5
50
ns
W5
t
AVWH
(t
AVEH
)
Address Setup to WE# (CE
X
) Going High
5
55
ns
W6
t
WHEH
(t
EHWH
)
CE
X
(WE#) Hold from WE# (CE
X
) High
10
ns
W7
t
WHDX
(t
EHDX
)
Data Hold from WE# (CE
X
) High
0
ns
W8
t
WHAX
(t
EHAX
)
Address Hold from WE# (CE
X
) High
0
ns
W9
t
WPH
Write Pulse Width High
6
30
ns
W11
t
VPWH
(t
VPEH
)
V
PEN
Setup to WE# (CE
X
) Going High
3
0
ns
W12
t
WHGL
(t
EHGL
)
Write Recovery before Read
7
35
ns
W13
t
WHRL
(t
EHRL
)
WE# (CE
X
) High to STS Going Low
8
500
ns
W15
t
QVVL
V
PEN
Hold from Valid SRD, STS Going High
3,8,9
0
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F128J3A 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Intel StrataFlash Memory
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