參數(shù)資料
型號(hào)： 28F128
廠商： Intel Corp.
英文描述： 3 Volt Intel StrataFlash Memory
中文描述： 3伏特英特爾StrataFlash存儲(chǔ)器
文件頁(yè)數(shù)： 18/58頁(yè)
文件大小： 380K
代理商： 28F128
28F128J3A, 28F640J3A, 28F320J3A
12
Preliminary
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command
Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set.
3. Bus operations are defined in
Table 3
.
4. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see
Figure 5
and
Table 15
.
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register. This data is presented to the device on A
16-1
; all
other address inputs
are ignored.
5. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See
Table 16
for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
CC = Configuration Code.
6. The upper byte of the data bus (DQ
DQ
) during command writes is a
“
Don
’
t Care
”
in x16 operation.
7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock
codes. See
Section 4.3
for read identifier code data.
8. If the WSM is running, only DQ
7
is valid; DQ
15
–
DQ
8
and DQ
6
–
DQ
0
float, which places them in a high-
impedance state.
9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
Table 4. Intel
StrataFlash
Memory Command Set Definitions
(1)
Command
Scalable or
Basic
Command
Set
(2)
Bus
Cycles
Req
’
d.
Notes
First Bus Cycle
Second Bus Cycle
Oper
(3)
Addr
(4)
Data
(5,6)
Oper
(3)
Addr
(4)
Data
(5,6)
Read Array
SCS/BCS
1
Write
X
FFH
Read Identifier Codes
SCS/BCS
≥
2
7
Write
X
90H
Read
IA
ID
Read Query
SCS
≥
2
Write
X
98H
Read
QA
QD
Read Status Register
SCS/BCS
2
8
Write
X
70H
Read
X
SRD
Clear Status Register
SCS/BCS
1
Write
X
50H
Write to Buffer
SCS/BCS
> 2
9, 10,
11
Write
BA
E8H
Write
BA
N
Word/Byte Program
SCS/BCS
2
12,13
Write
X
40H
or
10H
Write
PA
PD
Block Erase
SCS/BCS
2
11,12
Write
BA
20H
Write
BA
D0H
Block Erase, Program
Suspend
SCS/BCS
1
12,14
Write
X
B0H
Block Erase, Program
Resume
SCS/BCS
1
12
Write
X
D0H
Configuration
SCS
2
Write
X
B8H
Write
X
CC
Set Block Lock-Bit
SCS
2
Write
X
60H
Write
BA
01H
Clear Block Lock-Bits
SCS
2
15
Write
X
60H
Write
X
D0H
Protection Program
2
Write
X
C0H
Write
PA
PD
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F128J3A 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3 Volt Intel StrataFlash Memory
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