參數(shù)資料
型號: 24C02SC
廠商: Microchip Technology Inc.
英文描述: 2K 5.0V IIC serial EEPROMs(2.5V~5.5V,2K位,1M次擦寫周期,ISO7816標(biāo)準(zhǔn))
中文描述: 2K 5.0V國際進口電壓(2.5V?5.5V的和2K位,100萬次擦寫周期,符合ISO7816標(biāo)準(zhǔn)串行EEPROM)
文件頁數(shù): 80/170頁
文件大?。?/td> 4191K
代理商: 24C02SC
PIC16F62X
DS40300C-page 78
Preliminary
2003 Microchip Technology Inc.
FIGURE 12-9:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
FIGURE 12-10:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
FIGURE 12-11:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
START
BIT
BIT1
BIT0
BIT8
BIT0
STOP
BIT
START
BIT
BIT8
STOP
BIT
RB1/RX/DT (PIN)
RCV BUFFER REG
RCV SHIFT REG
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
WORD 1
RCREG
BIT8 = 0, DATA BYTE
BIT8 = 1, ADDRESS BYTE
1:
ADEN = 1
(ADDRESS MATCH
ENABLE)
'1'
'1'
Note
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and Bit 8 = 0.
START
BIT
BIT1
BIT0
BIT8
BIT0
STOP
BIT
START
BIT
BIT8
STOP
BIT
RB1/RX/DT (PIN)
REG
RCV BUFFER REG
RCV SHIFT
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
WORD 1
RCREG
BIT8 = 1, ADDRESS BYTE
BIT8 = 0, DATA BYTE
ADEN = 1
(ADDRESS MATCH
ENABLE)
'1'
'1'
Note
1:
This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.
START
BIT
BIT1
BIT0
BIT8
BIT0
STOP
BIT
START
BIT
BIT8
STOP
BIT
RB1/RX/DT (PIN)
REG
RCV BUFFER REG
RCV SHIFT
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
WORD 2
RCREG
BIT8 = 1, ADDRESS BYTE
BIT8 = 0, DATA BYTE
ADEN
(ADDRESS MATCH
ENABLE)
WORD 1
RCREG
Note
1:
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of
the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.
相關(guān)PDF資料
PDF描述
24C02A 2K 5.0V CMOS serial EEPROMs(2K位,5.0V,IIC串行EEPROM)
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