參數(shù)資料
型號(hào)： 24C02SC
廠商： Microchip Technology Inc.
英文描述： 2K 5.0V IIC serial EEPROMs(2.5V~5.5V,2K位,1M次擦寫周期,ISO7816標(biāo)準(zhǔn))
中文描述： 2K 5.0V國(guó)際進(jìn)口電壓（2.5V?5.5V的和2K位，100萬(wàn)次擦寫周期，符合ISO7816標(biāo)準(zhǔn)串行EEPROM）
文件頁(yè)數(shù)： 64/170頁(yè)
文件大?。?/td> 4191K
代理商： 24C02SC
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PIC16F62X
DS40300C-page 62
Preliminary
2003 Microchip Technology Inc.
11.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RB3/CCP1. An event is defined as:
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the Inter-
rupt Request Flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
11.1.1
CCP PIN CONFIGURATION
In Capture mode, the RB3/CCP1 pin should be
configured as an input by setting the TRISB<3> bit.
TABLE 11-2:
CAPTURE MODE OPERATION
BLOCK DIAGRAM
11.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
11.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in Operating mode.
11.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 11-1 shows the
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 11-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF CCP1CON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF CCP1CON ;Load CCP1CON with this
; value
11.2
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is:
Driven High
Driven Low
Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 11-1:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
11.2.1
CCP PIN CONFIGURATION
The user must configure the RB3/CCP1 pin as an
output by clearing the TRISB<3> bit.
Note:
If the RB3/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set flag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RB3/CCP1
Pin
Prescaler
3 1, 4, 16
and
edge detect
Note:
Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the
default low level. This is not the data latch.
CCPR1H CCPR1L
TMR1H
TMR1L
Comparator
Q
S
R
Output
Logic
Set flag bit CCP1IF
(PIR1<2>)
match
RB3/CCP1
Pin
TRISB<3>
Output Enable
CCP1CON<3:0>
Mode Select
Special Event Trigger will reset Timer1, but not set
interrupt flag bit TMR1IF (PIR1<0>)
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