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| 型號： | 24952 |
| 英文描述： | Interfacing the AMD-761? System Controller and the Via Technologies. Inc. VT82C686B Southbridge Application Note |
| 中文描述： | 接口的AMD - 761？系統(tǒng)控制器和威盛。公司VT82C686B南橋應(yīng)用筆記 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | 24952 |
4
Interfacing the AMD-761
System Controller and the Via Technologies, Inc. VT82C686B Southbridge
24952A
—
April 2001
I
The AMD-761 system controller implements WSC# as a
bidirectional pin that is first asserted by the Southbridge to
request that the posted write-buffers be snooped by the
processor, and subsequently asserted by the Northbridge to
indicate that the Southbridge
’
s IOAPIC can safely issue an
interrupt message to the local APIC. The AMD-761 system
controller does not assert the WSC# pin unless it first
receives a request on this pin.
The V T82C686B implements WSC# as a unidirectional pin
that is only driven by the Northbridge and must be asserted
low unless the Northbridge has outstanding PCI to DRAM
posted writes that have not been snooped by the processor.
When the V T82C686B is connected to an AMD-761 system
controller, the WSC# pin will never be asserted because the
V T82C686B does not first assert WSC# to request posted
writes to be snooped, thus the system is not able to send
interrupt messages to the processor.
I
Solution
Figure 2 shows an incompatible implementation where the
WSC# signal is directly connected between the A MD-761
System Controller and the V T82C686B.
Figure 2. Typical Configuration
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