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| 型號： | 24952 |
| 英文描述： | Interfacing the AMD-761? System Controller and the Via Technologies. Inc. VT82C686B Southbridge Application Note |
| 中文描述： | 接口的AMD - 761？系統(tǒng)控制器和威盛。公司VT82C686B南橋應(yīng)用筆記 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | 24952 |
3
24952A
—
April 2001
Interfacing the AMD-761
System Controller and the Via Technologies, Inc. VT82C686B Southbridge
Figure 1.
IOAPIC vs. Traditional PIC System Configuration
The mechanism typically employed in chipsets to flush the
posted write-buffers is a simple protocol between the
Northbridge and the Southbridge that signals the completion
of processor snooping of all posted write-buffers, indicating
that an interrupt message may be safely sent from the IOAPIC
to the local APIC. This mechanism is known as
“
Write Snoop
Complete
”
and is implemented with a pin called WSC#. The
WSC# pin is supported on both the AMD-761 system controller
and the V T82C686B Southbridge, but the implementations are
functionally incompatible as follows:
IOAPIC
I
nterrupt
Message Bus
3
CPU
Northbridge
Southbridge
PIC
INTR
CPU
Northbridge
Southbridge
Interrupt
Acknowledge Cycle
on PCI Bus
WSC#
IOAPIC System Configuration
Peripheral interrupt request occurs, IOAPIC must send
interrupt message to the processor
WSC# protocol forces Northbridge and CPU to snoop
all posted writes and provide a status indicator to the
Southbridge.
Southbridge/IOAPIC is now free to issue message to
CPU on the interrupt bus
Processor reads of memory are coherent.
PIC System Configuration
Peripheral interrupt request occurs, PIC sends inter-
rupt request to the processor on the INTR pin
Processor responds with interrupt acknowledge cycle
Interrupt acknowledge cycle forces Northbridge to
flush all posted writes.
Processor reads of memory are coherent.
1.
2.
3.
4.
Posted Writes
Posted Writes
Snoop
Snoop
1.
2.
3.
4.
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