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參數資料
| 型號： | 24952 |
| 英文描述： | Interfacing the AMD-761? System Controller and the Via Technologies. Inc. VT82C686B Southbridge Application Note |
| 中文描述： | 接口的AMD - 761？系統(tǒng)控制器和威盛。公司VT82C686B南橋應用筆記 |
| 文件頁數： | 6/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | 24952 |
2
Interfacing the AMD-761
System Controller and the Via Technologies, Inc. VT82C686B Southbridge
24952A
—
April 2001
Write Snoop Protocol
Incompatibility
Background
The Microsoft Windows
Logo Program Requirements 2.0 v.0.9
requires that all desk top systems must be A dvanced
Programmable Interrupt Controller (A PIC) enabled (SY S-
001.3). This requires that all hardware interrupts be connected
to the IOA PIC, and that the IOA PIC be connected to the
processor
’
s local A PIC. The communication between the
IOAPIC and the local A PIC occurs over a separate sideband
bus. A comparison of this configuration to the traditional PIC
configuration is shown in Figure 1 on page 3.
Operation with the IOAPIC and the local APIC requires all of
the Northbridge
’
s posted write-buffers to be properly flushed
to coherent memory before the IOA PIC sends an interrupt
message to the processor. This is required to prevent potential
data coherency problems that may result when the processor
receives an interrupt and reads stale data because the data
most recently written by the PCI Bus master still resides in a
posted wri te-buffer in the Northbridge. Non-A P IC
implementations do not have the potential for this problem
because the processor
’
s interrupt acknowledge cycle that
traverses the PCI Bus is serializing in nature, thus all posted-
write buffers are flushed before the processor reads memory in
the interrupt service routine.
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