參數(shù)資料
型號: 24952
英文描述: Interfacing the AMD-761? System Controller and the Via Technologies. Inc. VT82C686B Southbridge Application Note
中文描述: 接口的AMD - 761?系統(tǒng)控制器和威盛。公司VT82C686B南橋應(yīng)用筆記
文件頁數(shù): 10/12頁
文件大?。?/td> 102K
代理商: 24952
6
Interfacing the AMD-761
System Controller and the Via Technologies, Inc. VT82C686B Southbridge
24952A
April 2001
ACPI S3 Incompatibility with Registered DDR DIMMs
Background
Systems employing registered DDR DIMMs and the AMD-761
system controller/V T82C686B southbridge combination may
experience data corruption when entering or exiting the ACPI
S3 (Suspend to RAM) power management state. This is due to
an incompatibility in the sequencing of the PCIRESET# signal
between the Northbridge and the Southbridge.
Figure 4.
DDR DIMM Reset Connection in AMD-761 System Controller System
The AMD-761 system controller supports the ACPI S3 state by
specific sequencing on the DCSTOP# and PCIR E SE T# pins.
When entering the S3 state the DCSTOP# pin must be asserted
followed by the assertion of the PCIRE SET# pin one RTC clock
later (~30 mS). The PCIR E SE T # assertion is used by the
AMD-761 system controller to gate off its I/O pad ring since the
pad ring will be powered off while the core remains powered
(the DDR I/O pad ring remains powered). Approximately four
clocks later the DDR clocks will be disabled. Since registered
DIMMs incorporate PL L s and registers on the module, they
require a separate reset pin that must be asserted before its
clocks are removed to allow stable operation.
CPU
AMD-761
TM
System
Controller
VT82C686B
Southbridge
PCIRESET#
STPCLK#
Registered
DDR DIMMs
CLK
D
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