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參數(shù)資料
| 型號(hào)： | 24952 |
| 英文描述： | Interfacing the AMD-761? System Controller and the Via Technologies. Inc. VT82C686B Southbridge Application Note |
| 中文描述： | 接口的AMD - 761？系統(tǒng)控制器和威盛。公司VT82C686B南橋應(yīng)用筆記 |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | 24952 |
7
24952A
—
April 2001
Interfacing the AMD-761
System Controller and the Via Technologies, Inc. VT82C686B Southbridge
A s shown in Figure 4 on page 6, the reset pin on the DDR
DIMMs is connected to the Southbridge PCIR E SE T# pin in a
AMD-761 system controller-based system. When entering the
Suspend to R A M state, the A MD-761 system controller
continues to drive the DDR clocks for at least four clocks after
the PCIRST# pin is asserted to meet the DIMM requirements.
I
The V T82C686B does not follow the DCSTOP# and
PCIRESET# sequencing listed above. The V T82C686B does
not assert the PCIRESET# pin low until after the power
supply has been turned off (PWRGOOD de-asserted). This
means that the system clock generator is already powered
off by the time the AMD-761 system controller detects the
assertion of PCIRESET#. This potentially results in DDR
memory failures since the DIMM was not properly shut
down.
Solution
A solution for this incompatibility does not exist at this time.
A MD does not recommend the use of the A MD-761 system
controller with the V T 82C686B Southbridge in registered
DIMM applications.
Unbuffered DIMM applications using the A MD-761 system
controller with the V T82C686B Southbridge function properly.
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