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| 型號： | 24952 |
| 英文描述： | Interfacing the AMD-761? System Controller and the Via Technologies. Inc. VT82C686B Southbridge Application Note |
| 中文描述： | 接口的AMD - 761？系統(tǒng)控制器和威盛。公司VT82C686B南橋應(yīng)用筆記 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 102K |
| 代理商： | 24952 |
5
24952A
—
April 2001
Interfacing the AMD-761
System Controller and the Via Technologies, Inc. VT82C686B Southbridge
To alleviate this incompatibility, A MD recommends that the
WSC# signal be connected as shown in Figure 3. In this new
configuration, the motherboard must be designed in the
following fashion.
The WSC# pins of the AMD-761 system controller and the
V T82C686B
southbridge
unpopulated resistor pad shown as R1 in Figure 3. This
configuration allows POP/NOPOP capability. (A zero-ohm
resistor can be added in the event of silicon changes that
allow direct connection.)
Note:
The WSC# pin of the AMD-761 system controller contains
an internal pull-up resistor. No external termination is
required on the AMD-761 system controller WSC# pin when
it is disconnected from the VT82C686B WSC# input.
The WSC# input of the V T82C686B is terminated using a
resistor pad populated by a pull-down resistor shown as R2
in Figure 3. This configuration allows POP/NOPOP
capability for future changes.
I
are
connected
through
an
I
Figure 3. New Configuration
Note:
This solution only applies to uniprocessor applications using
the AMD-761 system controller.
Due to the shared IRQ architecture implemented by Windows
operating systems, the above solution provides proper
operation for Windows PC-2001 compliance. How A s ISR s
(Interrupt Service R outines) are invoked, the ISR s read the
status registers of the various devices to determine the source
of the interrupt. The reading of the status registers forces the
proper flushing of the posted write-buffers of the A MD-761
system controller before the local A PIC sends an interrupt
message to the processor. Hence, data coherency issues are
avoided.
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