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| 型號(hào)： | 23380A |
| 英文描述： | SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF) |
| 中文描述： | SDRAM的性能監(jiān)視器的？蘭？SC520微控制器？ 233KB（PDF格式） |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 233K |
| 代理商： | 23380A |
8
SDRAM Performance Monitors with the élanSC520 Microcontroller Application Note
Performance Monitoring Counters
Typically two large counters (i.e., 40 bits or more) are
provided for event counting. These counters can be
read and written from within the register address
space. The counters can be configured to measure
parameters such as the number of data reads that hit
in the cache. In this case, the second counter can be
programmed to record the number of actual data reads
performed. The ratio of these two numbers gives the
cache hit rate for reads.
When one of the counters reaches its limit, the overflow
signal can be used to stop all counting and generate an
interrupt. The software interrupt handler then records
the counter values and completes post data processing
and any other support work necessary.
The size of the counters is important. The larger the
counter, the less frequently an interrupt is generated.
Such interrupts are undesirable as they intrude into
normal processor operation. A larger counter also
results in greater data averaging. Any temporary
fluctuation in cache hit rate is not observed, and this
might be required.
Before performance monitoring can be accomplished,
an interrupt handler must be installed to process the
counter overflow. Of course, overflow can be avoided
by the use of extremely large counters. However, such
a technique can be expensive to implement, unreliable,
or fail to produce the desired statistical analysis.
Data Integration
The type of performance data being measured is
random in nature, such as the cache-hit rate or the
number of cycles to read memory. These parameters
vary during program execution. Measuring random
data enables a precise value to be generated for the
data examined. These precise values appear as
averages, such as the average cache-hit rate.
Measured performance parameters are a good esti-
mate of future performance. Actual performance at any
instant may vary widely from the measured estimate.
The typical use of two large counters does not measure
this deviation.
For example, at each memory access, an on-chip
cache can successfully provide the required data. The
sequence of hit and miss data can be represented by a
simple 1 or 0 bit stream, the probability of a 1 being the
probability of a hit occurring. A stochastic ADDIE can
be used to integrate the probability stream and deter-
mine the relevant probability.
Figure 2 shows a possible ADDIE configuration. A
counter is compared with a random number; if the
counter is bigger than the random number, a 1 is gen-
erated. Large counter values are more likely to produce
a 1 output from the comparator than small counter
values.
Figure 2.
Block Diagram of the ADDIE
The counter output is compared with the 1/0 data
stream type—the cache-hit information. These two
stochastic data streams are compared to determine
which one has the highest probability of being 1.
Determining this probability appears difficult; however,
only an XOR gate is required. When the data streams
Random Number
Comparator
Counter
AND
XOR
Clock
1 if Count > or = Random Number
Input Data Stream
0 1 0 1 Comparator
0 1 0 1 Input Data
0 1 0 1 XOR Output
Down
Up
Count Action
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