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| 型號： | 23380A |
| 英文描述： | SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF) |
| 中文描述： | SDRAM的性能監(jiān)視器的？蘭？SC520微控制器？ 233KB（PDF格式） |
| 文件頁數(shù)： | 5/18頁 |
| 文件大小： | 233K |
| 代理商： | 23380A |
SDRAM Performance Monitors with the élanSC520 Microcontroller Application Note
5
provided for the user to throttle the write request
interruptions to SDRAM. Because read-around-write
accesses are provided when the write buffer is
enabled, the watermark setting is provided to specify
how full the write buffer can become before requesting
service to write data back to SDRAM. The write buffer
requests SDRAM access when the configured
watermark is reached. The write buffer provides four
watermark settings. A higher watermark can be used to
delay write accesses from interfering with read
accesses by stalling write activity to SDRAM, which
also provides a greater chance of data write merging
and collapsing where a large amount of partial
DWORD writes are expected. A low watermark setting
can be used when the expected result is that most
writes to SDRAM are complete DWORDs, thus a
reduced chance of write buffer merging and collapsing
and the ECC read-modify-write cycles are not
necessary
. The user should configure the write buffer’s
watermark setting to a position that yields the lowest
write buffer full average.
Read Buffer Hit Monitoring
The élanSC520 microcontroller’s SDRAM controller
contains eight 4-byte read data buffers. When
combined, these buffers comprise the read buffer and
are designed to hold two cache lines of data that are
returned from SDRAM for transfers initiated by either
the Am5
x
86 CPU, PCI host bridge (on behalf of a PCI
master), or GP bus DMA. During any read request to
SDRAM, an entire cache line is always read into the
read buffer, independent of each read transfer being a
single DWORD, or a burst of two, three, or four
DWORDs. To maintain data coherency, any write
transfer to SDRAM on behalf of any master or the write
buffer that matches a cache line in the read buffer,
results in both cache lines of the read buffer being
invalidated. When the read prefetch feature is enabled
and the read request is a burst type (i.e., two or more
DWORDs), the entire cache line of the request
and
the
cache line following the requested cache line is also
fetched from SDRAM. The cache line following a single
DWORD read request is never prefetched; however,
the remainder of the requested DWORD’s cache line is
stored in the read buffer.
For example, if the Am5
x
86 CPU or PCI host bridge
requests a single DWORD of data from SDRAM, the
SDRAM controller fetches the entire cache line of data
on behalf of this single DWORD read request. The
requested DWORD is forwarded to the requesting
master, with the requested DWORD and remaining
DWORDs of that cache line being stored in the read
buffer. Any future accesses to the same cache line
within the read buffer result in read buffer hits.
Either of the two performance monitor resources can
be configured to provide a read buffer hit average of the
number of DWORD read transfers during either an
Am5
x
86 CPU, PCI host bridge, or GP bus DMA read
request that results in a hit to the read buffer. A read
buffer hit implies that at least one of the four bytes
within a DWORD resulted in a read buffer hit. The
performance monitor counts read buffer hits on the
basis of an atomic read request during the same bus
tenure, independent of burst length (i.e., complete
cycle, regardless of the amount of read data requested
during the same burst tenure). Therefore, each read
request
is monitored, instead of each DWORD
transferred, during that read request tenure. This
occurs because the read buffer always stores an entire
cache line of read data from SDRAM, independent of
the number of DWORDs requested during the read
request. A read request of two, three, or four DWORDs
that hit within the read buffer are counted by the
performance monitors as only one hit to the read buffer
because the read buffer always maintains an entire
cache line of data, and a hit of one DWORD during a
read burst request is guaranteed to hit the remaining
data in that cache line during that same bus tenure.
This occurs instead of unfairly counting four read buffer
hits during a burst of four DWORDs requested because
the entire cache line would result in a hit. Four
independent
read requests of one DWORD each result
in four independent read buffer hits by the performance
monitor because each read transfer is an individual
read request. A ratio of read buffer HIT/MISS is
provided by the performance monitors.
Read Buffer Hit Monitoring Analysis
The élanSC520 microcontroller’s SDRAM controller
maintains two cache lines of read data within the read
buffers. These buffers are always enabled. For any
read request, an entire cache line of data is stored in
the read buffer. When the SDRAM controller’s read
prefetch feature is enabled and the read request is a
burst type (i.e., two or more DWORDs), the entire
cache line that contains the requested data
and
the
cache line following the requested cache line are also
fetched from SDRAM. The read prefetch feature is
intended to accelerate SDRAM read accesses if read
requests are sequential, so that data is supplied to the
master while the next cache line from SDRAM is
concurrently prefetched, relying on sequential
accesses. The read buffers prefetch feature relies on
long tenure of a single requesting master, which can be
affected by the enable state of the Am5
x
86 CPU’s
cache, program flow, mastership changes, etc.
However, like all buffering techniques that speculatively
prefetch, the anticipated prefetched line might not be
used, possibly resulting in overhead associated with
the unused prefetch.
Either performance monitor can be used to provide a
read buffer hit average. This information can be used to
provide feedback to determine if the read prefetch
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