參數(shù)資料
型號(hào)： 23380A
英文描述： SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF)
中文描述： SDRAM的性能監(jiān)視器的？蘭？SC520微控制器？ 233KB（PDF格式）
文件頁(yè)數(shù)： 4/18頁(yè)
文件大?。?/td> 233K
代理商： 23380A
4
SDRAM Performance Monitors with the élanSC520 Microcontroller Application Note
large overhead associated with a write buffer flush prior
to every read request, the write buffer performs a read
merge data from the write buffer’s contents as data is
returned from SDRAM. Read merge occurs when a
read cycle hits a dirty DWORD that currently exists in
the write buffer and the read data returned from
SDRAM is replaced, or merged with existing bytes from
the write buffer. Read merging from the write buffer
occurs at the byte resolution.
For example, an Am5
x
86 CPU cache snoop that is a
result of a PCI host bridge read request requires a
cache line write-back that is a result of a hit in the
Am5
x
86 CPU’s write-back cache. First, the cache line
write-back data is written to the write buffer, followed by
the PCI Host Bridge read request to SDRAM, possibly
to more than one of the same four DWORD addresses
written during the cache line write-back. The cache line
write-back data is written to the write buffer, but the
read request from the PCI host bridge can be satisfied
by the SDRAM controller prior to the cache line write
data being actually written to SDRAM. Because the
write buffer supports read merging, the SDRAM data is
replaced by the more recent data from the write buffer
that was just written during the cache line write-back.
This feature enables the SDRAM controller to service
the demand of read requests overwrite cycles, without
the penalty of flushing the write buffer first.
Either of the two performance monitor resources can
be configured to provide a read merge average of the
number of DWORD read transfers during either an
Am5
x
86 CPU, PCI host bridge, or GP bus DMA read
request that results in a read merge from the write
buffer. A read merge implies that at least one of the four
bytes within a DWORD resulted in a read merge during
each
DWORD of a read request. Each DWORD of a
read transfer is monitored independently of each read
transfer being a single DWORD, or a burst of two, three,
or four DWORDs. A ratio of write buffer read-merge/no-
read-merge is provided by the performance monitors.
Write Buffer Read Merge Monitoring Analysis
Conventional write buffer architectures do not provide
the read merge function, and require the entire buffer
to be flushed to SDRAM if a read access occurs to any
data that currently exists in the buffer. When this
occurs, the read access incurs the overhead
associated with the write-back of
all
buffer contents to
SDRAM instead of just the data that is needed to
maintain data coherency. However, because the
élanSC520 microcontroller’s write buffer provides
merging and collapsing, this forced flush on the
occurrence of a read access that currently exists in the
write buffer is
not
necessary. The read access
continues around the associated write data, and the
more current write data is merged in from the write
buffer as the read data is being returned to the
requesting master from SDRAM.
Either performance monitor can be configured to pro-
vide a read merge average. This average can be used
to determine if the read-around-write feature of the
write buffer provides performance advantages.
Write Buffer Full Monitoring
The write buffer is intended to de-couple the master’s
write traffic from incurring the overhead associated with
SDRAM refresh cycles, page bank misses, and ECC
read-modify-write cycles as a result of incomplete
DWORD writes. When the write buffer is not full, write
data is posted in zero wait states. However, due to the
various delays mentioned above, data can be posted to
the write buffer faster than data is written to SDRAM.
This can result in a full write buffer such that no more
data can be posted until data is written from the write
buffer to SDRAM.
The write buffer’s watermark setting can play a role in
how often the write buffer becomes full. A higher water-
mark setting causes data to sit in the write buffer
longer, possibly enabling a write data merge or col-
lapse to occur, but delays requesting the SDRAM for
service for a write-back of write-buffered data to
SDRAM. A lower watermark setting requests SDRAM
service when less data is stacked into the write buffer.
Either of the two performance monitor resources can
be configured to provide a write buffer full average of
the number of write attempts by either an Am5
x
86
CPU, PCI host bridge, or GP bus DMA write request
that experienced the write buffer in a full state. A write
buffer full state implies that an attempt to write a
DWORD into the write buffer was stalled. Each
DWORD of a write transfer is monitored independently
of each write transfer being a single DWORD, or a burst
of two, three, or four DWORDs. A ratio of write buffer
full/not-full is provided by the performance monitors.
Write Buffer Full Monitoring Analysis
The write buffer provides 32 DWORDs of storage for
master write accesses to SDRAM. It is intended to
absorb the overhead associated with page and bank
misses during write cycles and ECC read-modify-write
cycles. The write buffer experiences a full condition
when master accesses write data into the write buffer
at a faster rate than data can be removed from the write
buffer into SDRAM. When full, master accesses will
experience delays associated with write accesses to
SDRAM.
Either performance monitor can be used to monitor the
write buffer full average, which can be used to
determine the best write buffer watermark setting and
also provide information regarding write overhead
associated with page and bank misses, and ECC read-
modify-write. The write buffer’s watermark settings are
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