參數(shù)資料
型號(hào)： 23380A
英文描述： SDRAM Performance Monitors with the ?lan?SC520 Microcontroller? 233KB (PDF)
中文描述： SDRAM的性能監(jiān)視器的？蘭？SC520微控制器？ 233KB（PDF格式）
文件頁數(shù)： 16/18頁
文件大?。?/td> 233K
代理商： 23380A
A-2
SDRAM Performance Monitors with the élanSC520 Microcontroller Application Note
Performance Monitor Control Register
MMCR Offset 44h
Memory-Mapped
(Preserved on Programmable Reset)
Register Description
This register selects the source to monitor for each of the two ADDIE machines.
Bit Definitions
7
6
5
4
3
2
1
0
Bit
Reserved
ADDIE1_SEL
Reserved
ADDIE0_SEL
Reset
0
0
0
0
0
0
0
0
R/W
RSV
R/W
RSV
R/W
Bit
Name
Function
7
Reserved
Reserved
This field should be written to a 0 for normal system operation.
6–4
ADDIE1_SEL
ADDIE 1 Selector
These bits select the source to monitor using ADDIE 1
000 = ADDIE 1 disabled
001 = SDRAM page-bank misses
010 = Write buffer hits
011 = Write buffer read merge hits
100 = Write buffer full
101 = Read buffer hits
110 = Reserved
111 = Reserved
3
Reserved
Reserved
This field should be written to a 0 for normal system operation.
2–0
ADDIE0_SEL
ADDIE 0 Selector
These bits select the source to monitor using ADDIE 0
000 = ADDIE 0 disabled
001 = SDRAM page-bank misses
010 = Write buffer hits
011 = Write buffer read merge hits
100 = Write buffer full
101 = Read buffer hits
110 = Reserved
111 = Reserved
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